There is provided a transistor comprising: a graphene layer structure provided on a non-metallic surface of a substrate, the graphene layer structure having an insulating cap; a source contact provided in contact with a first edge of the graphene layer structure; an insulator provided in contact with an opposite, second edge of the graphene layer structure; a drain contact provided in contact with the insulator, whereby there is a distance of least separation between the drain contact and the graphene layer structure along the second edge of the graphene layer structure and through the insulator; and a gate contact provided (i) over the graphene layer structure and separated therefrom by the insulating cap and/or (ii) under the graphene layer structure and separated therefrom by substrate.

The invention relates to a device comprising transistors (T1, T2, T3), each comprising: a channel (41) with the basis of a semiconductive material, a gate-all-around (50), totally surrounding said channel (41), a source (42) and a drain (43) on either side of the channel (41), and source and drain contacts (60S, 60, 60D), a gate dielectric layer (30) separating the channel (41) and the gate-all-around (50), spacers (70) on either side of the gate (50). Advantageously, the gate dielectric layer (30) and the spacers (70) are formed by at least one single and same continuous layer (73) surrounding the gate-all-around (50). The invention also relates to a method for producing such a device.

A non-volatile field-effect transistor includes a gate electrode including a first contact, a source comprising a second contact, a drain including a third contact, a channel between the drain and the source and formed by a two-dimensional electron gas, a remanent-state subassembly having two electrically controllable remanent states comprising at least one oxide layer, and a reducing layer made of at least one metal-type reducing material having an atomic concentration of metal elements greater than 50%. The application of a voltage between the first contact and another contact results in a non-volatile modulation of the conductivity of the two-dimensional gas.

A CMOS element includes an n-MOSFET and a p-MOSFET that share a common gate and a common drain. An n-type channel layer of the n-MOSFET is stacked so as to be located in a lower area with respect to the common gate, a p-type channel layer of the p-MOSFET is stacked so as to be located in an upper area with respect to the common gate, and the common drain is stacked so as to be located in a lateral area with respect to the common gate.

Disclosed are a high-mobility atomic layer semiconductor device based on modulation doping and a method for fabricating the same, which prevent a charge scattering phenomenon caused by ionized impurities by modulation doping dopants such that the dopants are spatially separated from a channel layer of an atomic layer semiconductor device having an atomic layer semiconductor heterojunction structure band-aligned. According to an embodiment of the present disclosure, a high-mobility atomic layer semiconductor device based on modulation doping includes a substrate, an atomic layer semiconductor heterojunction structure band-aligned in type I or type II and including a channel layer allowing movement of an electron and a doping layer, wherein the channel layer and the doping layer are stacked on the substrate, and a dopant formed on the doping layer and including a material for supplying an electron or a hole to the channel layer. The dopant is doped while being spatially separated from the channel layer through the doping layer, instead of being directly doped into the channel layer.

Provided are a method for preparing a nanotube array, a nanotube array and a device. The method includes: preparing a double-layer two-dimensional material with a relative angle of lattice orientations, which is used as a template; determining the chiral parameters of nanotubes to be prepared corresponding to the relative angle of the lattice orientations of the double-layer two-dimensional material, determining a nanoribbon orientation and a nanoribbon width according to the determined chiral parameters, determining the inter-nanoribbon spacing according to the density of the nanotubes to be prepared and the nanoribbon width, and etching the double-layer two-dimensional material according to the determined nanoribbon orientation, nanoribbon width and inter-nanoribbon spacing to obtain a nanoribbon array of the double-layer two-dimensional material; and performing thermal excitation treatment on the obtained nanoribbon array of the double-layer two-dimensional material to obtain a nanotube array. The present disclosure can prepare a nanotube array with controllable density, orientation and chirality.

A semiconductor structure includes: a substrate, a channel layer and a barrier layer which are stacked sequentially, the channel layer and the barrier layer including a gate region, and a source region and a drain region which are located on two sides of the gate region; a p-type semiconductor layer, located in the gate region; a first hydrogen-rich layer, located on a side, close to the drain region, of the p-type semiconductor layer, a hydrogen concentration of the first hydrogen-rich layer being greater than a hydrogen concentration of the p-type semiconductor layer; a gate, a source and a drain, where the gate is located on a side, away from the substrate, of the p-type semiconductor layer, the source is located in the source region, and the drain is located in the drain region.

One or more 3D transistor structures that use one or more 2D materials as transistor channels along with methods for fabricating the same are disclosed. A 3D transistor can include a first carrier nanosheet at least partially surrounded by a first 2D material and a second carrier nanosheet at least partially surrounded by a second 2D material. The transistor can include a first source/drain structure in electrical contact with a first end of the first 2D material and a first end of the second 2D material. The transistor can include a second source/drain structure in electrical contact with a second end of the first 2D material and a second end of the second 2D material. The transistor can include a gate structure at least partially surrounding the first 2D material and the second 2D material.

A method of fabricating a heterostructure includes forming a layered material structure such that the layered material structure has an edge, and growing epitaxially a nanostructure of layered material laterally from the edge of the layered material structure such that an inplane interface between the layered material structure and the nanostructure is defined. Growing the nanostructure is implemented at a growth temperature sufficiently near a decomposition temperature of the layered material such that a nucleation interface of the nanostructure has a single atomic configuration.

The present invention broadly relates to the fabrication and processing of graphene electronic devices on silicon which comprise a silicon dioxide passivation layer.