The present disclosure relates to vertical field effect transistors (FET). The vertical FET according to the invention includes a substrate (101) and a first electrode (102) configured as either a source or a drain of the transistor. The device includes a second electrode (104) configured as the other of the source and the drain, where the second electrode at least partially overlaps the first electrode in an overlapping region. Moreover, the device comprises an active layer (103) that is sandwiched between the first electrode and the second electrode and a gate arrangement including a gate conductor portion (107) and a gate insulating layer (106), which is arranged between the active layer (103) and a gate conductor portion (107) so as to prevent direct contact between the active layer (103) and the gate conductor portion (107). The active layer (103) comprises a 1D material arranged with its longitudinal axis parallel to the substrate (101) and/or a 2D material arranged with its plane substantially parallel to the substrate (101) The present disclosure further comprises a method (3000) for the manufacture of such vertical field effect transistors as well as for the manufacture of complementary logic devices.

The present disclosure relates to vertical field effect transistors (FET). The vertical FET according to the invention includes a substrate (101) and a first electrode (102) configured as either a source or a drain of the transistor. The device includes a second electrode (104) configured as the other of the source and the drain, where the second electrode at least partially overlaps the first electrode in an overlapping region. Moreover, the device comprises an active layer (103) that is sandwiched between the first electrode and the second electrode and a gate arrangement including a gate conductor portion (107) and a gate insulating layer (106), which is arranged between the active layer (103) and a gate conductor portion (107) so as to prevent direct contact between the active layer (103) and the gate conductor portion (107). The active layer (103) comprises a 1D material arranged with its longitudinal axis parallel to the substrate (101) and/or a 2D material arranged with its plane substantially parallel to the substrate (101) The present disclosure further comprises a method (3000) for the manufacture of such vertical field effect transistors as well as for the manufacture of complementary logic devices.

A trench-shaped ternary CMOS device includes a common drain provided at the bottom, a 2D phase change material layer composed of a 2D phase change material and stacked on the top of the common drain, a common gate provided over the 2D phase change material layer, a 2D n-type channel semiconductor material layer that is vertically stacked with respect to the 2D phase change material layer and connected to one end of the 2D phase change material layer and that has one side surface that faces one end of the common gate, and a 2D p-type channel semiconductor material layer that is vertically stacked with respect to the 2D phase change material layer and connected to an opposite end of the 2D phase change material layer and that has one side surface that faces an opposite end of the common gate.

The present disclosure relates to vertical field effect transistors (FET). The vertical FET according to the invention includes a substrate and a first electrode configured as either a source or a drain of the transistor. The device includes a second electrode) configured as the other of the source and the drain, where the second electrode at least partially overlaps the first electrode in an overlapping region. Moreover, the device comprises an active layer that is sandwiched between the first electrode and the second electrode and a gate arrangement including a gate conductor portion and a gate insulating layer, which is arranged between the active layer and a gate conductor portion as to prevent direct contact between the active layer and the gate conductor portion. The active layer comprises a 1D material arranged with its longitudinal axis parallel to the substrate and/or a 2D material arranged with its plane substantially parallel to the substrate. The present disclosure further comprises a method for the manufacture of such vertical field effect transistors as well as for the manufacture of complementary logic devices.

A semiconductor device including a semiconductor substrate, a lower metal contact disposed upon the semiconductor substrate, a gate structure disposed upon the lower metal contact, an upper metal contact disposed upon the gate structure, and a plurality of semiconductor carriers disposed in contact with both the lower metal contact and the upper metal contact, the plurality of semiconductor carriers disposed in channels passing through the gate structure.

A semiconductor device includes a substrate, a semiconductor layer disposed on the substrate, an insulating layer disposed on the semiconductor layer and having a first opening formed therein, a gate electrode disposed on the insulating layer and in contact with the semiconductor layer via the first opening, and a source electrode and a drain electrode in ohmic contact with the semiconductor layer. The gate electrode includes a crystallinity control film disposed on the insulating layer and having a second opening formed such that an inner wall thereof extends to an inner wall of the first opening toward the substrate in plan view in a direction perpendicular to a top surface of the substrate, and a first metal film disposed on the crystallinity control film and in Schottky contact with the semiconductor layer via the inner walls, extending to each other, of the second opening and the first opening.