A semiconductor device includes an insulating base layer, a plurality of semiconductor patterns stacked on the insulating base layer and spaced apart from each other, a gate structure surrounding the plurality of semiconductor patterns, first and second source/drain patterns disposed on the insulating base layer and connected to both side surfaces of the plurality of semiconductor patterns, respectively, a contact structure connected to first source/drain patterns through the insulating base layer, a sidewall insulating film disposed between an upper portion of the contact structure and an upper portion of the insulating base layer and extending onto a region of a portion of the gate structure located below a lowermost semiconductor pattern among the plurality of semiconductor patterns, and a power transmission line disposed on a lower surface of the insulating base layer and connected to the contact structure.

A semiconductor device may include a first active pattern, a second active pattern spaced apart at a first distance from the first active pattern, a third active pattern spaced apart at a second distance from the second active pattern, a first device isolation layer between the first and second active patterns, a second device isolation layer between the second and third active patterns, a first channel structure overlapping the first active pattern, a second channel structure overlapping the second active pattern, a third channel structure overlapping the third active pattern, and a separation dielectric layer between the first and second channel structures. The separation dielectric layer may overlap the first device isolation layer. A level of a top surface of the first device isolation layer may be higher than a level of a top surface of the second device isolation layer.

A semiconductor integrated circuit device includes a plurality of standard cells each having a nanosheet field effect transistor (FET). A first standard cell includes a first buried power rail extending in the X direction and a nanosheet FET having a first nanosheet extending in the X direction. A second standard cell includes a second buried power rail greater in size in the Y direction than the first buried power rail and a nanosheet FET having a second nanosheet greater in size in the Y direction than the first nanosheet.

A semiconductor memory cell includes a floating body region configured to be charged to a level indicative of a state of the memory cell. The floating body region is surrounded on all sides by gate region and may include a nanosheet FET, a multi-bridge-channel (MBC) FET, a nanoribbon FET or a nanowire FET. The floating body region is configured to have at least first and second stable states.

A semiconductor device includes a backside power delivery network (BSPDN). The semiconductor device includes a substrate, a first active pattern extending in a first direction, on a top surface of the substrate, a second active pattern extending in the first direction, and spaced apart from the first active pattern in a second direction intersecting the first direction, on the top surface of the substrate, a gate structure extending in the second direction, on the first active pattern and the second active pattern, a first source/drain pattern connected to the first active pattern, on a side surface of the gate structure, a second source/drain pattern connected to the second active pattern, on the side surface of the gate structure, back source/drain contacts penetrating the substrate, and a first power line connected to the back source/drain contacts on a bottom surface of the substrate.

Structures having stacked transistors with backside access are described. In an example, an integrated circuit structure includes a front side structure. The front side structure includes a device layer including first, second, third and fourth stacks of nanowires and corresponding first, second, third and fourth overlying gate lines, and the device layer including first, second, third, fourth and fifth source or drain structures and corresponding overlying trench contacts alternating with the stacks of nanowires and the overlying gate lines, and one or more metallization layers above the device layer. A backside structure includes a backside via connection coupled to a bottom portion of the third source or drain structure, the bottom portion of the third source or drain structure isolated from a top portion of the third source or drain structure.

A method of forming a comb-shaped transistor device is provided. The method includes forming a stack of alternating sacrificial spacer segments and channel segments on a substrate. The method further includes forming channel sidewalls on opposite sides of the stack of alternating sacrificial spacer segments and channel segments, and dividing the stack of alternating sacrificial spacer segments and channel segments into alternating sacrificial spacer slabs and channel slabs, wherein the channel slabs and channel sidewalls form a pair of comb-like structures. The method further includes trimming the sacrificial spacer slabs and channel slabs to form a nanosheet column of sacrificial plates and channel plates, and forming source/drains on opposite sides of the sacrificial plates and channel plates.

An integrated circuit comprising: a plurality of first gate electrodes extending in a second direction perpendicular to a first direction, wherein the plurality of first gate electrodes is in a first row that extends in the first direction; a first active pattern group comprising a plurality of first active patterns that extend in the first row in the first direction and intersecting the plurality of first gate electrodes; a plurality of second gate electrodes extending in the second direction in a second row that extends in the first direction; and a second active pattern group comprising a plurality of second active patterns extending in the second row in the first direction and intersecting the plurality of second gate electrodes, wherein ones of the plurality of first active patterns have different widths in the second direction, and the plurality of second active patterns have a first width in the second direction.

In an aspect, a semiconductor memory cell comprises gate structures separated by source or drain (S/D) structures, a frontside (FS) inter-layer dielectric (FS-ILD) layer above the gate and S/D structures, FS metal zero (FM0) interconnects above the FS-ILD layer, a backside (BS) inter-layer dielectric (BS-ILD) layer below the gate and S/D structures, BS metal zero (BM0) interconnects below the BS-ILD layer, at least one FS source drain contact (FSDC) electrically connecting an FM0 interconnect to a top surface of an S/D structure, and at least one BS S/D contact (BSDC) electrically connecting a BMO interconnect to a bottom surface of an S/D structure. The semiconductor memory cell comprises NFETs and PFETs to form a cross-coupled inverter pair. For each inverter in the pair, one of VDD and VSS are provided by an FSDC and the other of VDD and VSS is provided by a BSDC.

A semiconductor device and fabrication method are described for integrating a nanosheet transistor with a multimodal transistor (MMT) in a single nanosheet process flow by processing a wafer substrate to form buried metal source/drain structures in an MMT region that are laterally spaced apart from one another and positioned below an MMT semiconductor channel layer before forming a transistor stack of alternating Si and SiGe layers in an FET region which are selectively processed to form gate electrode openings so that a first ALD oxide and metal layer are patterned and etched to form gate electrodes in the transistor stack and to form a channel control gate electrode over the MMT semiconductor channel layer, and so that a second oxide and conductive layer are patterned and etched to form a current control gate electrode over the MMT semiconductor channel layer and adjacent to the channel control gate electrode.