A method of forming a portion of a gate-all-around field-effect transistor (GAA FET) nanosheet structure includes performing a trim back recess process to form recesses in inner spacers of a fin-shaped column in a first direction from a sidewall of the fin-shaped column, wherein the fin-shaped column includes a stack of nanosheet channels and sacrificial layers having the inner spacers on both sides thereof in the first direction, performing an interface epitaxial growth process to grow interface source/drain (S/D) epi layers from exposed surfaces of the nanosheet channels of the fin-shaped column on the sidewalls of the fin-shaped column, performing an etch back process to etch back the interface S/D epi layer and form a continuous surface of the interface S/D epi layer, and performing a full epitaxial growth process to fully grow an S/D epi layer from the continuous surface of the interface S/D epi layer.

One or more aspects of the present application relate to cooling management system implemented as part of an electric motor. Illustratively, the cooling management system corresponds to a sealed system/component that surrounding the motor stator magnetic core such that a cooling fluid is able to provide heat mitigation functionality during the operation of the AC induction motor, referred to generally as the electric motor. More specifically, illustratively, the cooling management system includes a reservoir configured to hold a cooling fluid, a pump configured to pump the cooling fluid, a heat exchanger configured to interact with the cooling fluid, and a sealed stator fluid jacket. The sealed stator fluid jacket further includes an over molded inner layer that defines an interior channel characterizing a space for the plurality of stator bars and that defines a plurality of flow channels for the flow of the cooling fluid.

A motor includes a stator core and a stator booster. The stator booster includes a booster back-iron and a plurality of booster teeth. The booster back-iron includes a first end surface that abuts a first end surface of the stator core's back-iron for electrical communication therewith. The booster teeth extend radially inward from the booster back-iron and are spaced apart from one another in a circumferential direction about the central axis to define a plurality of booster slots that align with slots of the stator core. A first end surface of each booster tooth abuts a first end surface of a corresponding tooth of the stator core for electrical communication therewith. An electrically insulating material encapsulates opposite sides of each booster tooth that define the booster slots and a second end surface of each booster tooth that is opposite the first end surface of that booster tooth.

A device includes a stator or a rotor configured to magnetically coupled through an air gap, a plurality of slots distributed along a perimeter of the stator or rotor, a plurality of metal bars each placed into one of the plurality of slots, and an end ring having plurality of openings. Each opening is configured to receive an end of one of the metal bars, and a lock feature is configured to improve a mechanical attachment between the end ring and the metal bar.

An integrated circuit device includes: a substrate including a first surface and a second surface that is opposite to the first surface; and a diode structure including: an upper semiconductor layer disposed on the first surface of the substrate and including a first dopant of a first conductivity type; a lower semiconductor layer disposed on the second surface of the substrate and including a second dopant of a second conductivity type that is different from the first conductivity type; and a first well region provided in a portion of the substrate that is between the upper semiconductor layer and the lower semiconductor layer, wherein the first well region is in contact with the upper semiconductor layer or the lower semiconductor layer.

An integrated circuit device includes: a rear insulating layer; a nanosheet stacked structure arranged on the rear insulating layer and including a plurality of nanosheets; a pair of source/drain regions positioned on sides of the nanosheet stacked structure in a first horizontal direction; a gate electrode extending in a second horizontal direction intersecting the first horizontal direction, on the nanosheet stacked structure; a contact plug connected to at least one of the pair of source/drain regions; a rear contact plug passing through the rear insulating layer and connected to at least one of the pair of source/drain regions; and a spacer layer including a contact spacer layer surrounding part of a side surface of the rear contact plug.

A semiconductor device is provided. The semiconductor device includes a substrate and channel structures stacked over each other along a first direction substantially perpendicular to a working surface of the substrate and each configured to have a current direction along a second direction substantially parallel to the working surface of the substrate. Source/drain (S/D) structures are positioned on opposing sides of the channel structure along the second direction. Gate structures are positioned on opposite sides of the channel structures along a third direction substantially parallel to the working surface of the substrate. The channel structures each have a shape of a nanosheet extending substantially perpendicular to the working surface of the substrate.

A method for producing a device comprising GAA transistors. Advantageously, the channels of the transistors are produced by deposition of a semiconductor material, preferably a 2D material, after successive removal of certain layers of the initial stack. The gates-all-around are produced after selective removal of the other layers from the initial stack. The initial stack does not comprise the semiconductor material, nor the material of the gates. The subsequent deposition of the semiconductor material aims to better preserve the semiconductor material.

A method for fabricating a GAA nanosheet structure, comprising: forming at least two channel layers and at least one sacrificial layer alternately stacked on a substrate to form a channel stack; forming, on the substrate, a dummy gate astride the channel stack; forming a first sidewall on a surface of the dummy gate; etching the sacrificial layer to form a recess at a side surface of the channel stack; forming a second sidewall within the recess; forming a source and a drain at two sides of the channel stack; in response to a channel layer being in contact with the dummy gate, etching the dummy gate and the channel layer to expose the at least one sacrificial layer, and then etching the at least one sacrificial layer to form a space for manufacturing a surrounding gate; and forming a metallic surrounding gate in the space.

A multi-gate hybrid-channel field-effect transistor (FET) structure of an integrated device like a nanosheet device or a forksheet device comprises a substrate layer, a first layer stack and a second layer stack arranged side by side on the substrate layer, a first and second additional semiconductor channel layer arranged respectively besides the second layer stack, and a dielectric wall arranged on the substrate layer between the first layer stack and the second layer stack. The first and second layer stack each comprise one or more semiconductor channel layers and gate layers stacked alternatingly with respective surfaces parallel to the surface of the substrate layer. Respective surfaces of the first and second additional semiconductor channel layer are parallel to each other and perpendicular to the surface of the substrate layer.