A semiconductor device structure is provided. The semiconductor device structure includes a source/drain (S/D) feature disposed over a substrate and between two adjacent semiconductor layers, an inner spacer disposed between and in contact with one semiconductor layer and the substrate, and a dielectric layer structure disposed between the S/D feature and the substrate. The dielectric layer structure includes a first dielectric layer in contact with the inner spacer and the substrate, and a second dielectric layer nested within the first dielectric layer, wherein a bottom surface and sidewall surfaces of the second dielectric layer are in contact with the first dielectric layer.

The present inventive concept provides a method of manufacturing an oxide transistor, the method comprising: a step of forming a first channel layer by supplying a gas containing indium (In) and zinc (Zn) and supplying a gas containing oxygen; a step of forming a spacer on the first channel layer by supplying a gas containing gallium (Ga) and supplying a gas containing oxygen; and a step of forming a second channel layer on the spacer by supplying a gas containing indium (In) and zinc (Zn) and supplying a gas containing oxygen, and an oxide transistor made by the method.

A semiconductor device fabrication method may comprise: alternately and sequentially stacking a source/drain electrode layer forming a source/drain and a channel layer forming an oxide semiconductor channel; stacking a mask layer to surround a portion where a source/drain region is to be formed; exposing a channel layer of a channel region by etching and removing the source/drain electrode layer of the channel region exposed through the mask layer; and sequentially forming a gate dielectric layer and at least one gate electrode layer on the exposed channel layer of the channel region and on exposed lateral sides of the source/drain electrode layer of the source/drain region.

A semiconductor device structure is provided. The semiconductor device structure includes a source/drain (S/D) feature disposed over a substrate and between two adjacent semiconductor layers, an inner spacer disposed between and in contact with one of the semiconductor layers and the substrate, and a dielectric layer structure disposed between the S/D feature and the substrate, the dielectric layer structure comprising a first dielectric layer in contact with the inner spacer and the substrate, and a second dielectric layer nested within the first dielectric layer, wherein a bottom surface and sidewall surfaces of the second dielectric layer are in contact with the first dielectric layer, and a bottom surface of the S/D feature, the first dielectric layer, the second dielectric layer, and the inner spacer define an air gap therebetween.

A vertical stack of three-dimensional transistors, such as nanoribbon-based transistors, includes a stack of nanoribbons with independent gates around subsets of nanoribbons in the stack. In previous nanoribbon transistors, a gate electrode wraps around all of the semiconductor regions and spans the areas between adjacent semiconductor regions, thus electrically coupling the centers of the semiconductor regions. To achieve a stack of semiconductor regions with independent gates, adjacent nanoribbons in the stack may be set at different distances apart, or two or more sacrificial materials may be included when forming the stack of semiconductor materials and selectively etched when forming different gates.

A semiconductor device includes a substrate, a lower channel stack on the substrate, an upper channel stack on the lower channel stack, a gate electrode extending around the lower channel stack and the upper channel stack, a gate cut region that is on the substrate and includes an insulating material, a semiconductor material layer between the upper channel stack and the gate cut region, and an insulating layer that is between the semiconductor material layer and the upper channel stack.

Embodiments of the invention include a single stack dual channel gate-all-around nanosheet with strained PFET and bottom dielectric isolation NFET. A PFET comprising at least one silicon germanium channel is formed. An NFET comprising at least one silicon channel is formed, the PFET being positioned laterally to the NFET, the at least one silicon channel and the at least one silicon germanium channel being staggered in a vertical direction.