Embodiments of the invention include a single stack dual channel gate-all-around nanosheet with strained PFET and bottom dielectric isolation NFET. A PFET comprising at least one silicon germanium channel is formed. An NFET comprising at least one silicon channel is formed, the PFET being positioned laterally to the NFET, the at least one silicon channel and the at least one silicon germanium channel being staggered in a vertical direction.

A transistor and a method for fabricating the transistor are provided. The semiconductor structure transistor includes a base, a low-dimensional material layer, a plurality of spacers, a source, a drain, and a gate stack. The low-dimensional material layer is provided above the base. The plurality of spacers is provided on a surface of the low-dimensional material layer away from the base and spaced apart from each other. The source and the drain are provided on the surface of the low-dimensional material layer away from the base, respectively. The gate stack is provided on the surface of the low-dimensional material layer away from the base and between the source and the drain, in which the gate stack, the source and the drain are separated by the spacers, and in contact with the spacers, respectively. Therefore, the transistor has advantages of excellent comprehensive performance, high process compatibility, and good device uniformity.

A source/drain contact of a nanostructure transistor is formed such that the source/drain contact is recessed within an underlying source/drain region of the nanostructure transistor using a multiple-step etching process. The source/drain contact being recessed within the source/drain region provides a greater amount of surface area for the source/drain contact to contact the source/drain region. This provides for increased contact surface area between the source/drain contact and the source/drain region, and the increased contact surface area provides for reduced contact resistance between the source/drain region and the source/drain contact, because of the less-restricted current flow path between the source/drain region and the source/drain contact. In this way, the reduced contact resistance between the source/drain region and the source/drain contact enables a greater power efficiency to be achieved for the nanostructure transistor and/or enables increased switching speeds to be achieved for the nanostructure transistor, among other examples.

The present disclosure provides a method that includes forming a stack including first and second semiconductor layers over a substrate, wherein the first and second semiconductor layers have different compositions and alternate with one another; patterning the stack to form active regions; forming an isolation structure to surround the active regions; forming a hard mask on the isolation structure; forming a dummy gate structure over the stack; recessing source/drain regions of the stack, resulting in source/drain trenches; selectively removing the second semiconductor layers, resulting in first gaps among the first semiconductor layers; forming dielectric interposers in the first gaps; performing a first etching process to laterally recess the dielectric interposers, resulting in second gaps; forming inner spacers in the second gaps; forming source/drain features in the source/drain trenches; removing the dummy gate structure; and removing a subset of the dielectric interposers while bottommost dielectric interposers remain.

A method includes forming a device layer over a substrate, the device layer comprising an upper transistor that is vertically stacked with a lower transistor; planarizing the substrate to expose a gate electrode of the lower transistor and a source/drain region of the lower transistor; and performing a directed self assembly (DSA) process to define a block of a first constituent polymer and a block of a second constituent polymer. The block of the first constituent polymer overlaps the gate electrode, and the block of the second constituent polymer overlaps the source/drain region. The method further includes replacing the block of the first constituent polymer with a dielectric material; and replacing the block of the second constituent polymer with a backside contact that is electrically connected to the source/drain region.