A method of forming a portion of a gate-all-around field-effect transistor (GAA FET) nanosheet structure includes performing a trim back recess process to form recesses in inner spacers of a fin-shaped column in a first direction from a sidewall of the fin-shaped column, wherein the fin-shaped column includes a stack of nanosheet channels and sacrificial layers having the inner spacers on both sides thereof in the first direction, performing an interface epitaxial growth process to grow interface source/drain (S/D) epi layers from exposed surfaces of the nanosheet channels of the fin-shaped column on the sidewalls of the fin-shaped column, performing an etch back process to etch back the interface S/D epi layer and form a continuous surface of the interface S/D epi layer, and performing a full epitaxial growth process to fully grow an S/D epi layer from the continuous surface of the interface S/D epi layer.

A semiconductor structure includes a substrate, a first transistor disposed over the substrate and including a first channel, a first interfacial layer over the first channel, a first gate dielectric layer over the first interfacial layer, and a first gate electrode layer over the first gate dielectric layer, and a second transistor disposed over the substrate and including a second channel, a second interfacial layer over the second channel, a second gate dielectric layer over the second interfacial layer, and a second gate electrode layer over the second gate dielectric layer. The first gate dielectric layer includes a first dipole material composition having a first maximum concentration at a half-thickness line of the first gate dielectric layer. The second gate dielectric layer includes a second dipole material composition having a second maximum concentration at a half-thickness line of the second gate dielectric layer and greater than the first maximum concentration.

Horizontal gate-all-around devices and methods of manufacturing are described. The hGAA devices include a fully-depleted silicon-on-insulator (FD-SOI) under the channel layers in the same footprint as the hGAA. The buried dielectric insulating layer of the FD-SOI includes one or more of silicon oxide (SiOx), silicon nitride (SiN), silicon carbide (SiC), and a high-k material, and the buried dielectric insulating layer has a thickness in a range of from 0 nm to 10 nm.

A method includes receiving a structure including a first region and a second region, forming a dielectric layer over the first region and the second region, forming a first patterned layer of a first dipole material on the dielectric layer in the first region, performing a first thermal drive-in operation to drive the first dipole material into the dielectric layer, forming a second patterned layer of a second dipole material on the dielectric layer in the second region, performing a second thermal drive-in operation to drive the second dipole material into the dielectric layer, performing a thermal operation to adjust distribution of the first dipole material or both the first and the second dipole materials in the dielectric layer, and forming a gate electrode layer over the dielectric layer. A portion of the first region overlaps with the second region.

Isolation breaks between logic cells in integrated circuit (IC) devices. A source-drain trench between adjacent channel regions includes a pair of source or drain semiconductor bodies, a first of the source or drain bodies in the source-drain trench is connected to a first of the channel regions, a second of the source or drain bodies in the source-drain trench is connected to a second of the channel regions, and a dielectric isolation is in the source-drain trench and between the pair of source or drain bodies. The dielectric isolation may include a void between layers or sidewalls of dielectric. The pair of source or drain bodies may include highly conductive, metallized layers in contact with the dielectric isolation.

A semiconductor device and fabrication method are described for integrating I/O and core nanosheet transistors in a single nanosheet process flow by processing a stack of alternating first and second semiconductor structures formed on a substrate, where the first semiconductor structures located over a I/O thick oxide transistor region include a planar semiconductor channel layer sandwiched between upper and lower dielectric layers, and where the alternating first and second semiconductor structures are processed to form gate-all-around electrodes in a core transistor stack that are connected over a relatively thinner gate dielectric layer to control one or more first planar semiconductor channel layers in the core transistor stack, and to form gate-all-around electrodes in an I/O transistor stack that are connected over a relatively thicker gate dielectric layer to control one or more second planar semiconductor channel layers in the I/O transistor stack.

Semiconductor structures and a method of forming the same are provided. In an embodiment, an exemplary semiconductor structure includes a doped region in a substrate and comprising a first-type dopant, a plurality of nanostructures disposed directly over the doped region, a gate structure wrapping around each nanostructure of the plurality of nanostructures, a first epitaxial feature and a second epitaxial feature coupled to the plurality of nanostructures, wherein each of the first epitaxial feature and the second epitaxial feature comprises the first-type dopant, a first insulation feature disposed between the first epitaxial feature and the doped region, and a second insulation feature disposed between the second epitaxial feature and the doped region.

Horizontal gate-all-around devices and methods of manufacturing are described. The hGAA devices include a fully-depleted silicon-on-insulator (FD-SOI) under the channel layers in the same footprint as the hGAA. The buried dielectric isolation layer of the FD-SOI includes one or more of silicon oxide (SiOx), silicon nitride (SiN), silicon carbide (SiC), and a high-k material, and the buried dielectric isolation layer has a thickness in a range of from 0 nm to 10 nm.

A source/drain component is disposed over an active region and surrounded by a dielectric material. A source/drain contact is disposed over the source/drain component. The source/drain contact includes a conductive capping layer and a conductive material having a different material composition than the conductive capping layer. The conductive material has a recessed bottom surface that is in direct contact with the conductive capping layer. A source/drain via is disposed over the source/drain contact. The source/drain via and the conductive material have different material compositions. The conductive capping layer contains tungsten, the conductive material contains molybdenum, and the source/drain via contains tungsten.

The present disclosure provides a semiconductor device and a method of forming the same. The semiconductor device includes a fin-shape base protruding from a semiconductor substrate. A top surface of the semiconductor substrate is in a (100) crystal plane, and a top surface of the fin-shape base is in a (110) crystal plane. The semiconductor device also includes channel members disposed over the top surface of the fin-shape base, a gate structure wrapping around at least one of channel members, a gate spacer extending along a sidewall of the gate structure, a source/drain feature abutting the channel members, and a dopant-free epitaxial feature under the source/drain feature. A top surface of the source/drain feature is in a (110) crystal plane. A top surface of the dopant-free epitaxial feature is in a (110) crystal plane.