Semiconductor devices and methods for forming the semiconductor devices using diffusion cap layers are provided. The semiconductor devices include a plurality of semiconductor layers vertically separated from one another, a gate structure that comprises a lower portion and an upper portion, wherein the lower portion wraps around each of the plurality of semiconductor layers, and a plurality of diffusion cap layers disposed between and separating the plurality of semiconductor layers and the gate structure. In some embodiments, the plurality of diffusion cap layers function as diffusion barriers for the plurality of semiconductor layers.

A semiconductor device and a method of fabricating the semiconductor device are disclosed. The semiconductor device includes a substrate, first and second nanostructured channel regions disposed on the substrate, a gate structure surrounding the first and second nanostructured channel regions, an inner gate spacer disposed along a sidewall of the gate structure and between the first and second nanostructured channel regions, and a source/drain (S/D) region. The S/D region includes an epitaxial liner disposed along sidewalls of the first and second nanostructured channel regions and the inner gate spacer and a germanium-based epitaxial region disposed on the epitaxial liner. The semiconductor further includes an isolation structure disposed between the germanium-based epitaxial region and the substrate.

Embodiments with present disclosure provides a gate-all-around FET device including a patterned or lowered bottom dielectric layer. The bottom dielectric layer prevents the subsequently formed epitaxial source/drain region from volume loss and induces compressive strain in the channel region to prevent strain loss and channel resistance degradation.

A semiconductor structure and fabrication method is provided for gate all around (GAA) nanosheet devices. The semiconductor structure comprises a substrate, a gate stack on the substrate with a plurality of gate regions and silicon-based channel regions alternatingly arranged one on the other. A length of the gate regions is smaller than a length of the channel regions. Thus, pockets are formed on a side of the gate stack, each pocket being arranged next to one gate region and between the two channel regions adjacent to the gate region. Further, a silicon-based first contact region extends in a distance to the side of the gate stack, and a silicon-based filler material is arranged between the first contact region and the first side of the gate stack and in each first pocket.

A semiconductor device includes: a gate structure having a side in a first direction and extending in a second direction intersecting the first direction; a source/drain region on the side of the gate structure; a plurality of channel layers spaced apart from each other in a third direction intersecting the first direction and the second direction and surrounded by the gate structure; and a plurality of inner spacers between the gate structure and the source/drain region, wherein the plurality of inner spacers have respective heights in the third direction increasing in the third direction toward bottom, and have respective thicknesses in the first direction decreasing in the third direction toward bottom.

A semiconductor device may include a substrate, a lower power line in a lower portion of the substrate, metal layers on the substrate, and a protection structure that is electrically connected to the lower power line and the metal layers. The protection structure may include a doping pattern in the substrate, and a first source/drain pattern that is on the substrate and is electrically connected to an upper portion of the doping pattern. The doping pattern and the first source/drain pattern may include different dopants from each other.

An integrated circuit device includes: a fin-type active region on a substrate; a nanosheet disposed on the fin-type active region; a gate line surrounding the nanosheet, wherein the gate line overlaps the nanosheet; a source/drain region disposed on the fin-type active region and contacting the nanosheet; and an interface insulating film surrounding the gate line, and including an inner spacer portion disposed between a sidewall of the gate line and the source/drain region, wherein the inner spacer portion includes: a first inner spacer portion protruding toward the source/drain region, while covering the sidewall of the gate line and while spaced apart from the nanosheet, wherein the first inner spacer portion has a first thickness; and a second inner spacer portion extending from the first inner spacer portion toward the nanosheet, wherein the second inner spacer portion has a second thickness that is less than the first thickness.

A semiconductor structure is provided. The semiconductor structure includes a first set of nanostructures that are stacked vertically and spaced apart from one another and formed in a first well, a source/drain feature adjoining the first set of nanostructures, a first top gate electrode layer above a topmost nanostructure in the first set of nanostructures, and an inner gate electrode layer sandwiched between the nanostructures. A first dimension of the inner gate electrode layer in a first direction is greater than a second dimension of the first top gate electrode layer in the first direction.

A semiconductor device and a method of fabricating the semiconductor device are disclosed. The semiconductor device includes a substrate, first and second nanostructured channel regions disposed on the substrate, a gate structure surrounding the first and second nanostructured channel regions, an inner gate spacer disposed along a sidewall of the gate structure and between the first and second nanostructured channel regions, and a source/drain (S/D) region. The S/D region includes an epitaxial liner disposed along sidewalls of the first and second nanostructured channel regions and the inner gate spacer and a germanium-based epitaxial region disposed on the epitaxial liner. The semiconductor further includes an isolation structure disposed between the germanium-based epitaxial region and the substrate.

A device includes a transistor. The transistor includes a plurality of stacked channels, a source/drain region coupled to the stacked channels, and a gate metal wrapped around the stacked channels. The transistor includes a plurality of inner spacers, each inner spacer being positioned laterally between the gate metal and the source/drain region and including a gap and an inner spacer liner layer between the gate metal and the source/drain region.