An electronic device having one or more non-planar transistors is disclosed. At least one of the non-planar transistors comprises: one or more gate structures; and one or more gate spacers associated with each of the one or more gate structures, at least one gate spacer of the one or more gate spacers having a multi-layer dielectric structure comprising an interior wall disposed next to a respective gate structure of the one or more gate structures, wherein the interior wall is formed from a first dielectric material, an exterior wall spaced apart from the interior wall, wherein the exterior wall is formed from a second dielectric material, and a third dielectric material disposed between the interior wall and the exterior wall, wherein a dielectric constant of the third dielectric material is lower than both the dielectric constants of the first and second dielectric materials.

A semiconductor device includes a first active pattern including a first lower pattern and first sheet patterns spaced apart from the first lower pattern in a first direction, a first gate structure including first inner gates between the first lower pattern and a lowermost first sheet pattern of the first sheet patterns, and between each pair of adjacent first sheet patterns, the first inner gates extending in a second direction that intersects the first direction, where each of the first inner gates includes a first gate electrode and a first gate insulating film, first source/drain patterns on the first lower pattern and connected to the first sheet patterns, first inner spacers between the first source/drain patterns and the first inner gates, and first nitrogen build-up areas within the first inner spacers.

Methods for fabricating semiconductor structures are provided. An exemplary method includes forming a first transistor structure and a second transistor structure over a substrate, wherein each transistor structure includes at least one nanosheet. The method further includes depositing a metal over each transistor structure and around each nanosheet; depositing a coating over the metal; depositing a mask over the coating; and patterning the mask to define a patterned mask, wherein the patterned mask lies over a masked portion of the coating and the second transistor structure, and wherein the patterned mask does not lie over an unmasked portion of the coating and the first transistor structure. The method further includes etching the unmasked portion of the coating and the metal over the first transistor structure using a dry etching process with a process pressure of from 30 to 60 (mTorr).

An integrated circuit device may include a nanosheet stack including a plurality of nanosheets, a gate line at least partially surrounding each of the plurality of nanosheets, the gate line including a main gate part and a sub-gate part, a source/drain region in contact with the plurality of nanosheets, and an inner insulating spacer between the sub-gate part and the source/drain region, wherein a first sidewall and a second sidewall each include a part recessed toward an inside of the inner insulating spacer, the first sidewall facing the source/drain and the second sidewall opposite to the first sidewall.

Methods for fabricating semiconductor structures are provided. An exemplary method includes forming a first transistor structure and a second transistor structure, wherein each transistor structure includes at least one channel region; depositing a work function material over the first transistor structure and the second transistor structure; and selectively removing the work function material from the first transistor structure while maintaining the work function material over the second transistor structure using a masked etching process, wherein after the selectively removing, the first transistor structure is free of the work function material and the second transistor structure retains the work function material.

A device includes a transistor. The transistor includes a plurality of stacked channels, a source/drain region coupled to the stacked channels, and a gate metal wrapped around the stacked channels. The transistor includes a plurality of inner spacers, each inner spacer being positioned laterally between the gate metal and the source/drain region and including a gap and an inner spacer liner layer between the gate metal and the source/drain region.

A semiconductor device structure is provided. The structure includes a gate dielectric layer disposed over a substrate, a gate electrode layer disposed over the gate dielectric layer, a plurality of semiconductor layers vertically stacked over the substrate, wherein the gate electrode layer surrounds a portion of each of the semiconductor layers, a first gate spacer disposed adjacent the gate dielectric layer, wherein the first gate spacer comprises an inner surface facing the gate dielectric layer and an outer surface opposite the inner surface, and the first gate spacer includes an oxygen concentration that decreases from the inner surface towards the outer surface, and a dielectric spacer disposed between two adjacent semiconductor layers of the plurality of semiconductor layers, wherein the dielectric spacer comprises an inner surface facing the gate dielectric layer and an outer surface opposite the inner surface, and the dielectric spacer includes an oxygen concentration that decreases from the inner surface towards the outer surface.

A method of manufacturing a semiconductor device includes forming an interfacial layer over a channel region and forming a metal-containing layer over the interfacial layer. A metal silicate layer is formed over the channel region after forming the metal-containing layer. A portion of the metal silicate layer is removed. A gate dielectric layer is formed over the channel region after removing the portion of the metal silicate layer, and a gate electrode layer is formed over the gate dielectric layer.

A method includes forming a fin protruding from a substrate, where the fin includes semiconductor layers interleaved with dielectric sacrificial layers. The method includes forming inner spacers at end portions of each of the dielectric sacrificial layers. The method includes forming source/drain features in the fin adjacent to the inner spacers. The method includes removing a portion of the fin between adjacent source/drain features to form a trench. The method includes forming an isolation structure in the trench.

The present disclosure provides semiconductor devices and methods of forming the same. A semiconductor device of the present disclosure includes a first source/drain feature and a second source/drain feature over a substrate, a plurality of channel members extending between the first source/drain feature and the second source/drain feature, a gate structure wrapping around each of the plurality of channel members, and at least one blocking feature. At least one of the plurality of channel members is isolated from the first source/drain feature and the second source/drain feature by the at least one blocking feature.