A semiconductor device includes a substrate, a first transistor unit having a first drain electrode, a first gate electrode, and a first source electrode, a second transistor unit having a second source electrode, a second gate electrode electrically, and a second drain electrode, a gate wiring provided on the substrate between the first source electrode and the second source electrode and electrically connected to the first gate electrode and the second gate electrode, a first cover metal layer provided above the substrate between the first source electrode and the gate wiring and adjacent to the first source electrode and the gate wiring, and electrically connected to the first source electrode, and a second cover metal layer provided above the substrate between the second source electrode and the gate wiring and adjacent to the second source electrode and the gate wiring, and electrically connected to the second source electrode.

A 3D semiconductor device, the device including: a first level including a first single crystal layer and including first transistors which each includes a single crystal channel; a first metal layer; a second metal layer overlaying the first metal layer; a second level including second transistors, first memory cells including at least one second transistor, and overlaying the second metal layer; a third level including third transistors and overlaying the second level; a fourth level including fourth transistors, second memory cells including at least one fourth transistor, and overlaying the third level, where at least one of the second transistors includes a metal gate, where the first level includes memory control circuits which control writing to the second memory cells, and at least one Phase-Lock-Loop (PLL) circuit or at least one Digital-Lock-Loop (DLL) circuit.

A metal oxide semiconductor field effect transistor (MOSFET) device and a manufacturing method therefor. A first implantation region easy to diffuse and a second implantation region which is not easy to diffuse and has a deeper junction are formed in sequence. After ion implantation in a source region and the like is completed, the first implantation region is activated to form a required well region in a mode of junction diffusion in the first implantation region, and the second implantation region is used for increasing the depth of the well region, thereby avoiding the damage to the surface of a substrate at a channel and roughness of the surface of the channel of the device caused by the formation of a P well directly through multiple Al ion implantation. Besides, the ion implantation in the first and second implantation regions, and the source region can use a same mask layer.

A method of forming a semiconductor device includes providing a precursor. The precursor includes a substrate; a gate stack over the substrate; a first dielectric layer over the gate stack; a gate spacer on sidewalls of the gate stack and on sidewalls of the first dielectric layer; and source and drain (S/D) contacts on opposing sides of the gate stack. The method further includes recessing the gate spacer to at least partially expose the sidewalls of the first dielectric layer but not to expose the sidewalls of the gate stack. The method further includes forming a spacer protection layer over the gate spacer, the first dielectric layer, and the S/D contacts.

A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a channel layer, an adhesion layer disposed over the channel layer, a first hafnium-containing dielectric layer disposed over the adhesion layer, a second hafnium-containing dielectric layer disposed over the first hafnium-containing dielectric layer, a gate structure, and source and drain terminals. The second hafnium-containing dielectric layer has a hafnium content lower than a hafnium content of the first hafnium-containing dielectric layer. A dielectric constant of the second hafnium-containing dielectric layer is larger than a dielectric constant of the first hafnium-containing dielectric layer.

A semiconductor device may include a source on a first side of a gate. The semiconductor device may include a drain on a second side of the gate, where the second side of the gate is opposite to the first side of the gate. The semiconductor device may include a first contact over the source. The semiconductor device may include a second contact over the drain. The semiconductor device may include an air gap over the gate between at least the first contact and the second contact. The semiconductor device may include at least two dielectric materials in each of a region between the air gap and the first contact and a region between the air gap and the second contact.

A CMOS inverter modified by implementing p-type doping regions in the inverter layout and during semiconductor wafer manufacturing creating a novel low resistivity shunt region in PWELLs preventing parasitic thyristor diodes from forward bias and eliminating latchup triggering. Latchup trigger can only occur when all thyristor diodes forward biased thereby establishing the parasitic current flow causing latchup. As voltage scales lower and temperature increases, latchup trigging doesn't recover and leads to a non-destructive stuck state in addition to catastrophic latch-up. The root cause of latch-up is high resistivity PWELLs. Shallow Buried Guard Ring (SBGR) doping application is a novel solution that solves the stuck state and prevents latchup thereby enabling digital circuits to operate in the most extreme environments without latching up and can be integrated without redesigning and through retrofit in commercial CMOS as well as in solar power procurement through photovoltaic cells.

Methods of forming and processing semiconductor devices which utilize a three-color hardmask process are described. Certain embodiments relate to the formation of self-aligned contacts for metal gate applications. More particularly, certain embodiments relate to the formation of self-aligned gate contacts through the selective deposition of a fill material.

A semiconductor chip includes a semiconductor body having a main surface and a rear surface opposite the main surface, a first bond pad disposed on the main surface, a second bond pad disposed on the rear surface, a first switching device that is monolithically integrated in the semiconductor body and has a first input-output terminal that is electrically connected to the first bond pad, and a second switching device that is monolithically integrated in the semiconductor body and has a first input-output terminal that is electrically connected to the second bond pad.

A nitride semiconductor device, including a substrate with a first nitride semiconductor layer on its surface, a block layer, an electron transit layer and an electron supply layer sequentially formed thereon. Formed along an inner surface thereof a first opening penetrating through the block layer to the first nitride semiconductor layer, a source electrode provided in a second opening in a location away from the first opening and connected to the block layer. The second opening penetrating through the electron supply and electron transit layers to the block layer. On an opposite surface of the substrate a drain electrode is provided. Seen in plan view, the first opening and the source electrode extend in a same, longitudinal direction, and the first opening includes: two straight portions extending in the longitudinal direction with the source electrode being interposed therebetween, and a first connection portion connecting ends of the two straight portions.