Various embodiments include methods and integrated circuit structures. In some cases, an integrated circuit (IC) structure includes: a substrate; a set of fin structures overlying the substrate, the set of fin structures including a substrate base and a silicide layer over the substrate base; an oxide layer located between adjacent fins in the set of fin structures; and a nitride layer over the set of fin structures, wherein a height of the nitride layer is substantially uniform across the set of fin structures.

A gate-all around fin double diffused metal oxide semiconductor (DMOS) devices and methods of manufacture are disclosed. The method includes forming a plurality of fin structures from a substrate. The method further includes forming a well of a first conductivity type and a second conductivity type within the substrate and corresponding fin structures of the plurality of fin structures. The method further includes forming a source contact on an exposed portion of a first fin structure. The method further comprises forming drain contacts on exposed portions of adjacent fin structures to the first fin structure. The method further includes forming a gate structure in a dielectric fill material about the first fin structure and extending over the well of the first conductivity type.

An integrated circuit device includes a pad layer having a body portion with a first doping type laterally adjacent to a drift region portion with a second doping type, a trench formed in the pad layer, the trench extending through an interface of the body portion and the drift region portion, a gate formed in the trench and over a top surface of the pad layer along the interface of the body portion and the drift region portion, an oxide formed in the trench on opposing sides of the gate, and a field plate embedded in the oxide on each of the opposing sides of the gate.

A semiconductor device comprises first stack of nanowires arranged on a substrate comprises a first nanowire and a second nanowire, the second nanowire is arranged substantially co-planar in a first plane with the first nanowire the first nanowire and the second nanowire arranged substantially parallel with the substrate, a second stack of nanowires comprises a third nanowire and a fourth nanowire, the third nanowire and the fourth nanowire arranged substantially co-planar in the first plane with the first nanowire, and the first nanowire and the second nanowire comprises a first semiconductor material and the third nanowire and the fourth nanowire comprises a second semiconductor material, the first semiconductor material dissimilar from the second semiconductor material.

A semiconductor structure includes a replacement strap for a finFET fin that provides communication between a storage capacitor and the fin. The storage capacitor is located in a deep trench formed in a substrate and the fin is formed on a surface of the substrate. The replacement strap allows for electrical connection of the fin to the storage capacitor and is in direct physical communication with the fin and the storage capacitor. The replacement strap may be formed by removing a sacrificial strap and merging epitaxially grown material from the fin and epitaxially grown material from the capacitor. The epitaxially grown material grown from the fin grows at a slower rate relative to the epitaxially grown material grown from the capacitor. By removing the sacrificial strap prior to forming the replacement strap, epitaxial overgrowth that may cause shorts between adjacent capacitors is limited.

A semiconductor device includes a semiconductor substrate, an element isolation film, and a fin having side surfaces facing each other in a first direction of an upper surface and a main surface connecting the facing side surfaces and extending in a second direction orthogonal to the first direction. The device further includes a control gate electrode arranged over the side surface via a gate insulation film and extending in the first direction, and a memory gate electrode arranged over the side surface via another gate insulation film having a charge accumulation layer and extending in the first direction. Furthermore, an overlap length by which the memory gate electrode overlaps with the side surface is smaller than an overlap length by which the control gate electrode overlaps with the side surface in the direction orthogonal to the upper surface.

A semiconductor device includes a substrate, at least one active region, at least one gate structure, and an insulating structure. The active region is present at least partially in the substrate. The gate structure is present on the active region. The gate structure has at least one end sidewall and a top surface intersecting to form a top interior angle. The top interior angle is an acute angle. The insulating structure is present adjacent to the end sidewall of the gate structure and on the substrate.

An asymmetric high-k dielectric for reduced gate induced drain leakage in high-k MOSFETs and methods of manufacture are disclosed. The method includes performing an implant process on a high-k dielectric sidewall of a gate structure. The method further includes performing an oxygen annealing process to grow an oxide region on a drain side of the gate structure, while inhibiting oxide growth on a source side of the gate structure adjacent to a source region.

A semiconductor device includes a semiconductor substrate having isolation regions formed therein and a fin-shaped semiconductor structure protruding vertically above the isolation regions and extending laterally in a first direction. The device additionally includes a gate dielectric wrapping a channel region of the fin-shaped semiconductor structure and a gate electrode wrapping the gate dielectric. The channel region is interposed in the first direction between a source region and a drain region and has sloped sidewalls and a width that continuously decreases from a base towards a peak of the channel region. The channel region comprises a volume inversion region having a height greater than about 25% of a total height of the channel region.

Embodiments of the present disclosure describe multi-threshold voltage devices and associated techniques and configurations. In one embodiment, an apparatus includes a semiconductor substrate, a channel body disposed on the semiconductor substrate, a first gate electrode having a first thickness coupled with the channel body and a second gate electrode having a second thickness coupled with the channel body, wherein the first thickness is greater than the second thickness. Other embodiments may be described and/or claimed.