A semiconductor device a method of forming the same are provided. The method includes forming a fin extending from a substrate and forming a gate dielectric layer along a top surface and sidewalls of the fin. A first thickness of the gate dielectric layer along the top surface of the fin is greater than a second thickness of the gate dielectric layer along the sidewalls of the fin.

A semiconductor structure includes a stack of semiconductor layers disposed over a substrate, a metal gate structure disposed over and interleaved with the stack of semiconductor layers, the metal gate structure including a gate electrode disposed over a gate dielectric layer, a first isolation structure disposed adjacent to a first sidewall of the stack of semiconductor layers, where the gate dielectric layer fills space between the first isolation structure and the first sidewall of the stack of semiconductor layers, and a second isolation structure disposed adjacent to a second sidewall of the stack of semiconductor layers, where the gate electrode fills the space between the second isolation structure and the second sidewall of the stack of semiconductor layers.

Semiconductor devices are provided. In one example, a semiconductor device includes: a substrate, a first circuit region and a second circuit region extending in a first direction, and a gate structure extending in a second direction that is substantially perpendicular to the first direction. The gate structure further includes: two gate electrode sections respectively located in the first and second circuit regions, and a low-resistance section between and interconnecting the two gate electrode sections. The two gate electrode sections are configured as gate electrodes for two transistors respectively located in the first and second circuit regions. The two gate electrodes have a first width (W.sub.0) along the first direction, the low-resistance section has a second width (W) along the first direction, and a ratio of W to W.sub.0 (W/W.sub.0) is at least 1.1.

A vertical field-effect transistor. The transistor includes: a drift region having a first conductivity type; a semiconductor fin on or over the drift region; and a source/drain electrode on or over the semiconductor fin, the semiconductor fin having an electrically conductive region that connects the source/drain electrode to the drift region in electrically conductive fashion, and having a limiting structure that is formed laterally next to the electrically conductive region and that extends from the source/drain electrode to the drift region, the limiting structure being set up to limit a conductive channel of the vertical field-effect transistor in the semiconductor fin to the area of the electrically conductive region.

An asymmetric high-k dielectric for reduced gate induced drain leakage in high-k MOSFETs and methods of manufacture are disclosed. The method includes performing an implant process on a high-k dielectric sidewall of a gate structure. The method further includes performing an oxygen annealing process to grow an oxide region on a drain side of the gate structure, while inhibiting oxide growth on a source side of the gate structure adjacent to a source region.

A device includes: a gate line on an active region of a substrate, a pair of source/drain regions in the active region on both sides of the gate line, a contact plug on at least one source/drain region out of the pair of source/drain regions; and a multilayer-structured insulating spacer between the gate line and the contact plug. The multilayer-structured insulating spacer may include an oxide layer, a first carbon-containing insulating layer covering a first surface of the oxide layer adjacent to the gate line, and a second carbon-containing insulating layer covering a second surface of the oxide layer, opposite to the first surface of the oxide layer, adjacent to the contact plug.

A nonplanar semiconductor device having a semiconductor body formed on an insulating layer of a substrate. The semiconductor body has a top surface opposite a bottom surface formed on the insulating layer and a pair of laterally opposite sidewalls wherein the distance between the laterally opposite sidewalls at the top surface is greater than at the bottom surface. A gate dielectric layer is formed on the top surface of the semiconductor body and on the sidewalls of the semiconductor body. A gate electrode is formed on the gate dielectric layer on the top surface and sidewalls of the semiconductor body. A pair of source/drain regions are formed in the semiconductor body on opposite sides of the gate electrode.

Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a fin structure over a semiconductor substrate. The semiconductor device structure also includes a gate stack covering a portion of the fin structure. The gate stack includes a first portion and a second portion adjacent to the fin structure, and the first portion is wider than the second portion.

An asymmetric high-k dielectric for reduced gate induced drain leakage in high-k MOSFETs and methods of manufacture are disclosed. The method includes performing an implant process on a high-k dielectric sidewall of a gate structure. The method further includes performing an oxygen annealing process to grow an oxide region on a drain side of the gate structure, while inhibiting oxide growth on a source side of the gate structure adjacent to a source region.

A semiconductor device includes a semiconductor substrate, an element isolation film, and a fin having side surfaces facing each other in a first direction of an upper surface and a main surface connecting the facing side surfaces and extending in a second direction orthogonal to the first direction. The device further includes a control gate electrode arranged over the side surface via a gate insulation film and extending in the first direction, and a memory gate electrode arranged over the side surface via another gate insulation film having a charge accumulation layer and extending in the first direction. Furthermore, an overlap length by which the memory gate electrode overlaps with the side surface is smaller than an overlap length by which the control gate electrode overlaps with the side surface in the direction orthogonal to the upper surface.