A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes: a first conductive type buried layer disposed on a substrate; a first conductive type deep well region, a second conductive type body region, and a first conductive type drift region which are disposed on the first conductive type buried layer; a source region disposed in the second conductive type body region; a drain region disposed in the first conductive type deep well region; and a gate electrode disposed on the second conductive type body region and the first conductive type drift region.

The present disclosure relates to semiconductor structures and, more particularly, to metal-oxide semiconductor transistors and methods of manufacture. The structure includes: a substrate comprising a drift region and a body region; a gate structure between the drift region and the body region; an insulator material over the gate structure, the drift region and the body region; and an air gap within the insulator material and extending into the drift region.

An integrated circuit structure includes a semiconductor substrate, a first source/drain feature, a second source/drain feature, a gate dielectric layer, a gate electrode, a field plate electrode, and a dielectric layer. The semiconductor substrate has a well region and a drift region therein. The first source/drain feature is in the well region. The second source/drain feature is in the semiconductor substrate. The drift region is between the well region and the second source/drain feature. The gate dielectric layer is over the well region and the drift region. The gate electrode is over the gate dielectric layer and vertically overlapping the well region. The field plate electrode is over the gate dielectric layer and vertically overlapping the drift region. The dielectric layer is between the gate electrode and the field plate electrode. A top surface of the gate electrode is free of the dielectric layer.

A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes: a first conductive type buried layer disposed on a substrate; a first conductive type deep well region, a second conductive type body region, and a first conductive type drift region which are disposed on the first conductive type buried layer; a source region disposed in the second conductive type body region; a drain region disposed in the first conductive type deep well region; and a gate electrode disposed on the second conductive type body region and the first conductive type drift region.

A method for eliminating divot formation includes forming an isolation layer; forming a conduction layer which has an upper inclined boundary with the isolation layer such that the conduction layer has a portion located above a portion of the isolation layer at the upper inclined boundary; etching back the isolation layer; and etching back the conduction layer after etching back the isolation layer such that a top surface of the etched conduction layer is located at a level lower than a top surface of the etched isolation layer.

An object of the present invention is to further improve electric characteristics such as ON-resistance or an ON-breakdown voltage in a semiconductor device having a lateral MOS transistor. In a semiconductor device having a lateral MOS transistor, a buried electrode is formed at a part of an isolation insulating film located between a drain region and a gate electrode. The buried electrode includes a buried part. The buried part is formed from the surface of the isolation insulating film up to a depth corresponding to a thickness thinner than that of the isolation insulating film. The buried electrode is electrically coupled to the drain region.

A high-voltage MOS transistor includes a semiconductor substrate, a gate oxide layer on the semiconductor substrate, a gate on the gate oxide layer, a spacer covering a sidewall of the gate, a source on one side of the gate, and a drain on the other side of the gate. The gate includes at least a first discrete segment and a second discrete segment. The first discrete segment is not in direct contact with the second discrete segment. The spacer fills into a gap between the first discrete segment and the second discrete segment.

In an embodiment, a semiconductor device includes a semiconductor substrate having a bulk resistivity 100 Ohm.cm, a front surface and a rear surface, at least one LDMOS transistor in the semiconductor substrate, and a RESURF structure. The RESURF structure includes a doped buried layer arranged in the semiconductor substrate, spaced at a distance from the front surface and the rear surface, and coupled with at least one of a channel region and a body contact region of the LDMOS transistor.

A lateral superjunction MOSFET device includes multiple transistor cells connected to a lateral superjunction structure, each transistor cell including a conductive gate finger, a source region finger, a body contact region finger and a drain region finger arranged laterally within each transistor cell. Each of the drain region fingers, the source region fingers and the body contact region fingers is a doped region finger having a termination region at an end of the doped region finger. The lateral superjunction MOSFET device further includes a termination structure formed in the termination region of each doped region finger and including one or more termination columns having the same conductivity type as the doped region finger and positioned near the end of the doped region finger. The one or more termination columns extend through the lateral superjunction structure and are electrically unbiased.

A power integrated circuit includes a double-diffused metal-oxide-semiconductor (LDMOS) transistor formed in a first portion of the semiconductor layer with a channel being formed in a first body region. The power integrated circuit includes a first deep diffusion region formed in the first deep well under the first body region and in electrical contact with the first body region and a second deep diffusion region formed in the first deep well under the drain drift region and in electrical contact with the first body region. The first deep diffusion region and the second deep diffusion region together form a reduced surface field (RESURF) structure in the LDMOS transistor.