The present disclosure relates to semiconductor structures and, more particularly, to an extended drain metal oxide semiconductor (EDMOS) field effect transistor (FET) with a fully depleted region comprising a dual thicknesses semiconductor material and methods of manufacture. The structure includes: a semiconductor on insulator (SOI) material including a first portion with a first thickness and a second portion with a second thickness; a gate structure on the SOI material over the first portion with the first thickness; and sidewall spacers adjacent to the gate structure, with at least one sidewall spacer extending over both the first portion with the first thickness and the second portion with the second thickness.

A high-voltage switching device that can be fabricated in a standard low-voltage process, such as CMOS, and more specifically SOI CMOS. Embodiments include integrated circuits that combine, in a unitary structure, a FET device and an integrated, co-fabricated modulated resistance region (MRR) controlled by one or more Voltage-Drop Modulation Gates (VDMGs). The VDMGs are generally biased independently of the gate of the FET device, and in such a way as to protect each VDMG from excessive and potentially destructive voltages. In a first embodiment, an integrated circuit high voltage switching device includes a transistor structure including a source, a gate, and an internal drain; an MRR connected to the internal drain of the transistor structure; at least one VDMG that controls the resistance of the MRR; and a drain electrically connected to the MRR. Each VDMG at least partially depletes the MRR upon application of a bias voltage.

A semiconductor structure includes a substrate assembly and a semiconductor device. The semiconductor device is formed on the substrate assembly, and includes a body region, two active regions, and a butted body. The active regions are disposed at two opposite sides of the body region, and both have a first type conductivity. The body region and the active regions together occupy on a surface region of the substrate assembly. The butted body has a second type conductivity different from the first type conductivity, and is located on the surface region of the substrate assembly so as to permit the body region to be tied to one of the active regions through the butted body.

A semiconductor structure, the semiconductor structure includes a substrate with a first conductivity type and a laterally diffused metal-oxide-semiconductor (LDMOS) device on the substrate, the LDMOS device includes a first well region on the substrate, and the first well region has a first conductivity type. A second well region with a second conductivity type, the second conductivity type is complementary to the first conductivity type, a source doped region in the second well region with the first conductivity type, and a deep drain doped region in the first well region, the deep drain doped region has the first conductivity type.

The present disclosure describes a structure with a conductive plate and a method for forming the structure. The structure includes a gate structure disposed on a diffusion region of a substrate, a protective layer in contact with the diffusion region and covering a sidewall of the gate structure and a portion of a top surface of the gate structure, and a first insulating layer in contact with the gate structure and the protective layer. The structure further includes a conductive plate in contact with the first insulating layer, where a first portion of the conductive plate laterally extends over a horizontal portion of the protective layer, and where a second portion of the conductive plate extends over a sidewall portion of the protective layer covering the sidewall of the gate structure. The structure further includes a second insulating layer in contact with the conductive plate.

A high voltage semiconductor device includes a semiconductor substrate, an isolation structure, a gate oxide layer, and a gate structure. The semiconductor substrate includes a channel region, and at least a part of the isolation structure is disposed in the semiconductor substrate and surrounds the channel region. The gate oxide layer is disposed on the semiconductor substrate, and the gate oxide layer includes a first portion and a second portion. The second portion is disposed at two opposite sides of the first portion in a horizontal direction, and a thickness of the first portion is greater than a thickness of the second portion. The gate structure is disposed on the gate oxide layer and the isolation structure.

Structures for an extended-drain metal-oxide-semiconductor device and methods of forming a structure for an extended-drain metal-oxide-semiconductor device. The structure comprises a semiconductor layer, a source region, a drain region, and a gate positioned between the source region and the drain region. The gate includes a gate conductor layer, a first gate dielectric layer having a first thickness, and a second gate dielectric layer having a second thickness greater than the first thickness. The first gate dielectric layer is disposed on a top surface of the semiconductor layer, and the second gate dielectric layer includes a first section on the top surface of the semiconductor layer and a second section adjacent to a sidewall of the semiconductor layer. The gate conductor layer has an overlapping relationship with the first gate dielectric layer, the first section of the second gate dielectric layer, and the second section of the second gate dielectric layer.

A SiC semiconductor device having high pressure resistance properties is disclosed. The present invention provides a SiC semiconductor device comprising: a SiC substrate having a first surface and a second surface; an insulating area formed on the second surface side inside the SiC substrate; and a plurality of semiconductor areas including a source area, a base area, and a drain area formed along the first surface on the insulating area, wherein the SiC semiconductor device has a P/N junction parallel to the first surface, the P/N junction extending from the base area toward the drain area on the insulating area and being formed by a first auxiliary region of a first conductive type which is the same conductive type as the source area and a second auxiliary region of a second conductive type which is opposed to the first conductive type.

A semiconductor structure includes a substrate assembly and a semiconductor device. The semiconductor device is formed on the substrate assembly, and includes a body region, two active regions, and a butted body. The active regions are disposed at two opposite sides of the body region, and both have a first type conductivity. The body region and the active regions together occupy on a surface region of the substrate assembly. The butted body has a second type conductivity different from the first type conductivity, and is located on the surface region of the substrate assembly so as to permit the body region to be tied to one of the active regions through the butted body.

An object of the present invention is to further improve electric characteristics such as ON-resistance or an ON-breakdown voltage in a semiconductor device having a lateral MOS transistor. In a semiconductor device having a lateral MOS transistor, a buried electrode is formed at a part of an isolation insulating film located between a drain region and a gate electrode. The buried electrode includes a buried part. The buried part is formed from the surface of the isolation insulating film up to a depth corresponding to a thickness thinner than that of the isolation insulating film. The buried electrode is electrically coupled to the drain region.