The subject matter disclosed herein relates to semiconductor power devices, such as silicon carbide (SiC) power devices. In particular, the subject matter disclosed herein relates to shielding regions in the form of channel region extensions for that reduce the electric field present between the well regions of neighboring device cells of a semiconductor device under reverse bias. The disclosed channel region extensions have the same conductivity-type as the channel region and extend outwardly from the channel region and into the JFET region of a first device cell such that a distance between the channel region extension and a region of a neighboring device cell having the same conductivity type is less than or equal to the parallel JFET width. The disclosed shielding regions enable superior performance relative to a conventional stripe device of comparable dimensions, while still providing similar reliability (e.g., long-term, high-temperature stability at reverse bias).

The subject matter disclosed herein relates to semiconductor power devices, such as silicon carbide (SiC) power devices. In particular, the subject matter disclosed herein relates to disconnected or connected shielding regions that reduce the electric field present between the well regions of neighboring device cells of a semiconductor device under reverse bias. The disclosed shielding regions occupy a widest portion of the JFET region between adjacent device cells such that a distance between a shielding region and well regions surrounding device cell is less than a parallel JFET width between two adjacent device cells, while maintaining a channel region width and/or a JFET region density that is greater than that of a comparable conventional stripe device. As such, the disclosed shielding regions and device layouts enable superior performance relative to a conventional stripe device of comparable dimensions, while still providing similar reliability (e.g., long-term, high-temperature stability at reverse bias).

The subject matter disclosed herein relates to silicon carbide (SiC) power devices. In particular, the present disclosure relates to shielding regions for use in combination with an optimization layer. The disclosed shielding regions reduce the electric field present between the well regions of neighboring device cells of a semiconductor device under reverse bias. The disclosed shielding regions occupy a portion of the JFET region between adjacent device cells and interrupt the continuity of the optimization layer in a widest portion of the JFET region, where the corners of neighboring device cells meet. The disclosed shielding regions and device layouts enable superior performance relative to a conventional stripe device of comparable dimensions, while still providing similar reliability (e.g., long-term, high-temperature stability at reverse bias).

A p-type base region, n.sup.+-type source region, p.sup.+-type contact region, and n-type JFET region are formed on a front surface side of a silicon carbide base by ion implantation. The front surface of the silicon carbide base is thermally oxidized, forming a thermal oxide film. Activation annealing at a high temperature of 1500 degrees C. or higher is performed with the front surface of the silicon carbide base being covered by the thermal oxide film. The activation annealing is performed in a gas atmosphere that includes oxygen at a partial pressure from 0.01 atm to 1 atm and therefore, the thermal oxide film thickness may be maintained or increased without a decrease thereof. The thermal oxide film is used as a gate insulating film and thereafter, a poly-silicon layer that is to become a gate electrode is deposited on the thermal oxide film, forming a MOS gate structure.

In one general aspect, an apparatus can include a silicon carbide (SiC) device can include a gate dielectric, a first doped region having a first conductivity type, a source, a body region of the first conductivity type, and a second doped region having a second conductivity type. The second doped region can have a first portion and a second portion. The first portion can be disposed between the first doped region and the body region and the second portion can be disposed between the first doped region and the gate dielectric. The first portion of the second doped region can have a width less than a width of the first doped region.

A power semiconductor device includes a silicon carbide substrate and at least a first layer or region formed above the substrate. The silicon carbide substrate has a pattern of pits formed thereon. The device further comprising an ohmic metal disposed at least in the pits to form low-resistance ohmic contacts.

Methods of forming a semiconductor structure include the use of channeled implants into silicon carbide crystals. Some methods include providing a silicon carbide layer having a crystallographic axis, heating the silicon carbide layer to a temperature of about 300 C. or more, implanting dopant ions into the heated silicon carbide layer at an implant angle between a direction of implantation and the crystallographic axis of less than about 2, and annealing the silicon carbide layer at a time-temperature product of less than about 30,000 C.-hours to activate the implanted ions.

A semiconductor device may include a drift region having a first conductivity type, a source region having the first conductivity type, and a well region having a second conductivity type disposed adjacent to the drift region and adjacent to the source region. The well region may include a channel region that has the second conductivity type disposed adjacent to the source region and proximal to a surface of the semiconductor device cell. The channel region may include a non-uniform edge that includes at least one protrusion.

A method for manufacturing a semiconductor device, includes: (a) providing a SiC epitaxial substrate in which on a SiC support substrate, a SiC epitaxial growth layer having an impurity concentration equal to or less than 1/10,000 of that of the SiC support substrate and having a thickness of 50 m or more is disposed; (b) forming an impurity region, which forms a semiconductor element, on a first main surface of the SiC epitaxial substrate by selectively injecting impurity ions; (c) forming an ion implantation region, which controls warpage of the SiC epitaxial substrate, on a second main surface of the SiC epitaxial substrate by injecting predetermined ions; and (d) heating the SiC epitaxial substrate after (b) and (c).

A semiconductor device includes a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type provided on a part of the first semiconductor region, a third semiconductor region of the first conductivity type provided on a part of the second semiconductor region, agate electrode, a first electrode, and a conductive portion. The gate electrode is provided on another part of the second semiconductor region via a gate insulating portion. The first electrode is provided on the third semiconductor region and electrically connected to the third semiconductor region. The conductive portion is provided on another part of the first semiconductor region via a first insulating portion and electrically connected to the first electrode, and includes a portion arranged side by side with the gate electrode in a second direction perpendicular to a first direction from the first semiconductor region to the first electrode.