In one embodiment, a power MOSFET cell includes an N+ silicon substrate having a drain electrode. An N-type drift layer is grown over the substrate. An N-type layer, having a higher dopant concentration than the drift region, is then formed along with a trench having sidewalls. A P-well is formed in the N-type layer, and an N+ source region is formed in the P-well. A gate is formed over the P-well's lateral channel and has a vertical extension into the trench. A positive gate voltage inverts the lateral channel and increases the vertical conduction along the sidewalls to reduce on-resistance. A vertical shield field plate is also located next to the sidewalls and may be connected to the gate. The field plate laterally depletes the N-type layer when the device is off to increase the breakdown voltage. A buried layer and sinker enable the use of a topside drain electrode.

A lateral trench MOSFET comprises an insulating layer buried in a substrate, a body region in the substrate, an isolation region in the substrate, a first drain/source region over the body region, a second drain/source region in the substrate, wherein the first drain/source region and the second drain/source region are on opposing sides of the isolation region, a drift region comprising a first drift region of a first doping density formed between the second drain/source region and the insulating layer, wherein the first drift region comprises an upper portion surrounded by isolation regions and a lower portion and a second drift region of a second doping density formed between the isolation region and the insulating layer, wherein a height of the second drift region is equal to a height of the lower portion of the first drift region.

A vertical semiconductor device (e.g. a vertical power device, an IGBT device, a vertical bipolar transistor, a UMOS device or a GTO thyristor) is formed with an active semiconductor region, within which a plurality of semiconductor structures have been fabricated to form an active device, and below which at least a portion of a substrate material has been removed to isolate the active device, to expose at least one of the semiconductor structures for bottom side electrical connection and to enhance thermal dissipation. At least one of the semiconductor structures is preferably contacted by an electrode at the bottom side of the active semiconductor region.

This composite substrate has a single-crystal semiconductor thin film (13) provided to at least the front surface of an inorganic insulating sintered-body substrate (11) having a thermal conductivity of at least 5 W/m.Math.K and a volume resistivity of at least 110.sup.8 .Math.cm. The composite substrate also has, provided between the inorganic insulating sintered-body substrate (11) and the single-crystal semiconductor thin film (13), a silicon coating layer (12) comprising polycrystalline silicon or amorphous silicon. As a result of the present invention, metal impurity contamination from the sintered body can be inhibited, even in a composite substrate in which a single-crystal silicon thin film is provided upon an inexpensive ceramic sintered body which is opaque with respect to visible light, which exhibits an excellent thermal conductivity, and which further exhibits little loss at a high frequency range, and characteristics can be improved.

A lateral trench MOSFET comprises an insulating layer buried in a substrate, a body region in the substrate, an isolation region in the substrate, a first drain/source region over the body region, a second drain/source region in the substrate, wherein the first drain/source region and the second drain/source region are on opposing sides of the isolation region, a drift region comprising a first drift region of a first doping density formed between the second drain/source region and the insulating layer, wherein the first drift region comprises an upper portion surrounded by isolation regions and a lower portion and a second drift region of a second doping density formed between the isolation region and the insulating layer, wherein a height of the second drift region is equal to a height of the lower portion of the first drift region.

A representative method for fabricating a field effect transistor comprises forming a source region and a drain region disposed in a substrate; forming a gate structure over the substrate, the gate structure comprising sidewalls and a top surface, the gate structure interposing the source region and the drain region; forming a contact etch stop layer (CESL) over at least a portion of the top surface of the gate structure; forming an interlayer dielectric layer over the CESL; forming a gate contact extending through the interlayer dielectric layer; and forming a source contact and a drain contact extending through the interlayer dielectric layer, wherein a first distance between an edge of the source contact and a first corresponding edge of the CESL is about 1 nm to about 10 nm.

A vertical semiconductor device (e.g. a vertical power device, an IGBT device, a vertical bipolar transistor, a UMOS device or a GTO thyristor) is formed with an active semiconductor region, within which a plurality of semiconductor structures have been fabricated to form an active device, and below which at least a portion of a substrate material has been removed to isolate the active device, to expose at least one of the semiconductor structures for bottom side electrical connection and to enhance thermal dissipation. At least one of the semiconductor structures is preferably contacted by an electrode at the bottom side of the active semiconductor region.

A transistor switch device is provided that exhibits relatively good voltage capability and relatively easy drive requirements to turn the device on and off. This can reduce transient drive current flows that may perturb other components.

A transistor switch device is provided that exhibits relatively good voltage capability and relatively easy drive requirements to turn the device on and off. This can reduce transient drive current flows that may perturb other components.

A bidirectional Metal-Oxide-Semiconductor (MOS) device, including a P-type substrate, and an active region. The active region includes a drift region, a first MOS structure and a second MOS structure; the first MOS structure includes a first P-type body region, a first P+ contact region, a first N+ source region, a first metal electrode, and a first gate structure; the second MOS structure includes a second P-type body region, a second P+ contact region, a second N+ source region, a second metal electrode, and a second gate structure; and the drift region includes a dielectric slot, a first N-type layer, a second N-type layer, and an N-type region. The active region is disposed on the upper surface of the P-type substrate. The first MOS structure and the second MOS structure are symmetrically disposed on two ends of the upper layer of the drift region.