A high-voltage switching device that can be fabricated in a standard low-voltage process, such as CMOS, and more specifically SOI CMOS. Embodiments include integrated circuits that combine, in a unitary structure, a FET device and an integrated, co-fabricated modulated resistance region (MRR) controlled by one or more Voltage-Drop Modulation Gates (VDMGs). The VDMGs are generally biased independently of the gate of the FET device, and in such a way as to protect each VDMG from excessive and potentially destructive voltages. In a first embodiment, an integrated circuit high voltage switching device includes a transistor structure including a source, a gate, and an internal drain; an MRR connected to the internal drain of the transistor structure; at least one VDMG that controls the resistance of the MRR; and a drain electrically connected to the MRR. Each VDMG at least partially depletes the MRR upon application of a bias voltage.

A semiconductor device and the method of manufacturing the same are provided. The semiconductor device comprises a well region, a first doped region, a drain region, a source region and a gate electrode. The first doped region of a first conductivity type is located at a first side within the well region. The drain region of the first conductivity type is within the first doped region. The source region of the first conductivity type is at a second side within the well region, wherein the second side being opposite to the first side. The gate electrode is over the well region and between the source region and the drain region. A surface of the drain region and a surface of the source region define a channel and the surface of the source region directly contacts the well region.

A semiconductor device and the method of manufacturing the same are provided. The semiconductor device comprises a well region, a first doped region, a drain region, a source region and a gate electrode. The first doped region of a first conductivity type is located at a first side within the well region. The drain region of the first conductivity type is within the first doped region. The source region of the first conductivity type is at a second side within the well region, wherein the second side being opposite to the first side. The gate electrode is over the well region and between the source region and the drain region. A surface of the drain region and a surface of the source region define a channel and the surface of the source region directly contacts the well region.

A field effect transistor (FET) with raised source/drain region of the device so as to constrain the epitaxial growth of the drain region. The arrangement of the spacer layer is created by depositing a photoresist over the extended drain layer during a photolithographic process.

Disclosed are methods that employ a mask with openings arranged in a pattern of elongated trenches and holes of varying widths to achieve a linearly graded conductivity level. These methods can be used to form a lateral double-diffused metal oxide semiconductor field effect transistor (LDMOSFET) with a drain drift region having an appropriate type conductivity at a level that increases essentially linearly from the body region to the drain region. Furthermore, these methods also provide for improve manufacturability in that multiple instances of this same pattern can be used during a single dopant implant process to implant a first dopant with a first type (e.g., N-type) conductivity into the drain drift regions of both first and second type LDMOSFETs (e.g., N and P-type LDMOSFETs, respectively). In this case, the drain drift region of a second type LDMOSFET can subsequently be uniformly counter-doped. Also disclosed are the resulting semiconductor structures.

The present invention provides a manufacture method of a LTPS thin film transistor and a LTPS thin film transistor. The gate isolation layer is first etched to form the recess, and then the gate is formed on the recess so that the width of the gate is slightly larger than the width of the recess. Then, the active layer is implemented with ion implantation to form the source contact region, the drain contact region, the channel region and one transition region at least located between the drain contact region and the channel region. The gate isolation layer above the transition region is thicker than the channel region and can shield a part of the gate electrical field to make the carrier density here lower than the channel region to form a transition.

According to an embodiment, a semiconductor device is provided. The device includes a second region having a greater curvature than a first region. The device includes an epitaxy layer of a first conductivity type, a well of a second conductivity type in the epitaxy layer, a drain in the epitaxy layer, a source in the well, and a bulk in the well and in contact with the source, the bulk having a greater area in the second region than in the first region.

A quasi-lateral diffusion transistor is formed in a semiconductor-on-insulator (SOI) wafer by forming a gate region, a body region, a drift region, and a source region and bonding a handle wafer to the SOI wafer at a first side (e.g., top side) of the SOI wafer; and removing a semiconductor substrate of the SOI wafer, forming a hole in a buried insulator layer of the SOI wafer, and forming a drain region for the transistor at a second side (e.g., bottom side) of the SOI wafer. The body region and the drift region physically contact the buried insulator layer. The drain region is formed in a bottom portion of the drift region exposed by the hole and is laterally offset from the source region. In operation of the quasi-lateral diffusion transistor, a current flow direction through the semiconductor layer is diagonal between the source region and the drain region.

The disclosure provides a manufacturing method for TFT array substrate, a TFT array substrate and a display device. The manufacturing method includes following steps: in sequence, forming a gate pattern layer, a gate insulating layer, a patterned poly-silicon layer, a separation layer on s substrate, and adopting a mask to form a source pattern layer and a drain pattern layer on the separation layer by photolithography processes. The source pattern layer and the drain pattern layer are connected to the patterned poly-silicon layer. The mask blocks one side of the channel area, and the same mask is adopted to form a lightly doped area on the other side of the channel area not blocked by the mask. The disclosure may reduce production costs and has great design flexibility.

The present invention provides a manufacture method of a LTPS thin film transistor and a LTPS thin film transistor. The gate isolation layer is first etched to form the recess, and then the gate is formed on the recess so that the width of the gate is slightly larger than the width of the recess. Then, the active layer is implemented with ion implantation to form the source contact region, the drain contact region, the channel region and one transition region at least located between the drain contact region and the channel region. The gate isolation layer above the transition region is thicker than the channel region and can shield a part of the gate electrical field to make the carrier density here lower than the channel region to form a transition.