Related to the field of display panels, an array substrate, a manufacturing method thereof, and a display panel. The array substrate includes: the base substrate, the buffer layer, the active layer, the gate insulation layer, the gate, the interlayer insulation layer, the source, and the drain, which are stacked together. By using the gate insulation layer as a conductive mask of the active layer, and by adjusting the width of the gate and the width of the gate insulation layer, a width difference between the channel region and the gate is within the preset range, which reduces the problem of excessive width difference caused by the diffusion phenomenon of the channel region, and can at the same time meet the switching characteristics requirements of the thin film transistor and the definition requirements of the display panel.

Provided is an electro-optical device including a transistor, a pixel electrode provided on a light incidence side of the transistor, a lens layer provided in a layer between the transistor and the pixel electrode, and a relay layer serving as a first relay layer that is provided in a layer between the lens layer and the pixel electrode and electrically connected to the pixel electrode, wherein the relay layer includes WSi on the pixel electrode side.

The present disclosure provides an array substrate and a display device. The array substrate includes: a plurality of gate lines extending in a first direction, and a plurality of data lines extending in a second direction and crossing the gate lines to define a plurality of sub-pixels; a plurality of touch signal lines extending in the second direction and arranged in light shielding regions of the sub-pixels; a plurality of touch electrodes insulated from each other; and a plurality of metal pattern units corresponding to the sub-pixels respectively and arranged in the light shielding region of each sub-pixel. The metal pattern unit includes a first metal strip arranged on at least one side of the data line and extending in the second direction.

Disclosed is a display device that is capable of being driven with low power consumption. A first thin-film transistor including a polycrystalline semiconductor layer and a second thin-film transistor including an oxide semiconductor layer are disposed in an active area, thereby reducing power consumption. At least one opening formed in a bending area is formed to have the same depth as any one of contact holes formed in the active area, thereby making it possible to form the opening and the contact holes through the same process and consequently simplifying the process of manufacturing the device. A second source electrode of the second thin-film transistor and a second gate electrode of the second thin-film transistor overlap each other with an upper interlayer insulation film interposed therebetween so as to form a first storage capacitor.

A thin film transistor according to an exemplary embodiment of the present invention includes an oxide semiconductor. A source electrode and a drain electrode face each other. The source electrode and the drain electrode are positioned at two opposite sides, respectively, of the oxide semiconductor. A low conductive region is positioned between the source electrode or the drain electrode and the oxide semiconductor. An insulating layer is positioned on the oxide semiconductor and the low conductive region. A gate electrode is positioned on the insulating layer. The insulating layer covers the oxide semiconductor and the low conductive region. A carrier concentration of the low conductive region is lower than a carrier concentration of the source electrode or the drain electrode.

A 3-dimensional array of NOR memory strings being organized by planes of NOR memory strings, in which (i) the storage transistors in the NOR memory strings situated in a first group of planes are configured to be programmed, erased, program-inhibited or read in parallel, and (ii) the storage transistors in NOR memory strings situated within a second group of planes are configured for storing resource management data relating to data stored in the storage transistors of the NOR memory strings situated within the first group of planes, wherein the storage transistors in NOR memory strings in the second group of planes are configured into sets.

A thin film transistor includes a gate, a source, a drain, and an active layer. The active layer includes first and second oxide layers that are stacked, the source and the drain are both disposed at a side of the second oxide layer away from the first oxide layer, the first oxide layer is a crystalline oxide layer, and the second oxide layer is a lanthanide oxide layer. When the gate is disposed at a side of the first oxide layer away from the second oxide layer, an atomic proportion of an indium element in the first oxide layer is greater than that of the second oxide layer; when the gate is disposed at the side of the second oxide layer away from the first oxide layer, the atomic proportion of the indium element in the first oxide layer is less than that of the second oxide layer.

A method for manufacturing a semiconductor device, the method comprising steps of: forming a first metal oxide layer containing aluminium as a main component above an insulating surface; performing a planarization process on a surface of the first metal oxide layer; forming an oxide semiconductor layer on the insulating surface on which the planarization process is performed; forming a gate insulating layer above the oxide semiconductor layer; and forming a gate electrode facing the oxide semiconductor layer above the gate insulating layer.

A thin film transistor includes a metal oxide layer over the substrate, an oxide semiconductor layer having crystallinity in contact with the metal oxide layer, a gate electrode overlapping the oxide semiconductor layer, and an insulating layer between the oxide semiconductor layer and the gate electrode. The oxide semiconductor layer includes a plurality of crystal grains. Each of the plurality of crystal grains includes at least one of a crystal orientation <001>, a crystal orientation <101>, and a crystal orientation <111> obtained by an EBSD method. In occupancy rates of crystal orientations calculated based on measurement points having crystal orientations with a crystal orientation difference greater than or equal to 0 degrees and less than or equal to 15 degrees with respect to a normal direction of a surface of the substrate, an occupancy rate of the crystal orientation <001> is less than or equal to 5%.

An oxide semiconductor film having crystallinity over a substrate contains indium (In) and a first metal element (M1). The oxide semiconductor film includes a plurality of crystal grains. Each of the plurality of crystal grains includes at least one of a crystal orientation <001>, a crystal orientation <101>, and a crystal orientation <111> obtained by an electron backscatter diffraction (EBSD) method. In occupancy rates of crystal orientations calculated based on measurement points having crystal orientations with a crystal orientation difference greater than or equal to 0 degrees and less than or equal to 15 degrees with respect to a normal direction of a surface of the substrate, an occupancy rate of the crystal orientation <111> is greater than an occupancy rate of the crystal orientation <001> and an occupancy rate of the crystal orientation <101>.