According to one embodiment, a method of manufacturing a semiconductor device, includes forming a first insulating layer, an oxide semiconductor layer, a second insulating layer, a buffer layer and a metal layer sequentially on a base, forming a patterned resist on the metal layer, etching the buffer layer and the metal layer using the resist as a mask to expose an upper surface of the second insulating layer, reducing a volume of the resist to expose an upper surface along a side surface of the metal layer, etching the metal layer using the resist as a mask, to form a gate electrode and to expose an upper surface of the buffer layer, and carrying out ion implantation on the oxide semiconductor layer using the gate electrode as a mask.

A method includes forming a first and a second gate dielectric on a first semiconductor channel region and a second semiconductor channel region overlapping the first semiconductor region, forming a first dipole film on the first gate dielectric, wherein the first dipole film comprises a first dipole dopant of a first type, and forming a second dipole film on the second gate dielectric. A drive-in process is performed to drive dipole dopants in the first dipole film and the second dipole film into the first gate dielectric and the second gate dielectric, respectively. The first dipole film and the second dipole film are removed. A gate electrode is formed on both of the first gate dielectric and the second gate dielectric to form a first transistor and a second transistor.

A semiconductor device includes a substrate, a gate electrode in the substrate, a channel region above the gate electrode, a gate dielectric layer between the gate electrode and the channel region, and at least two source/drain regions in contact with the channel region. The channel region includes at least one boron-carbon-nitrogen single-walled nanotube (BCN-SWNT).

A method of forming a semiconductor device comprises the following steps. A dielectric layer is formed over a substrate. A 2D material layer is formed over the dielectric layer. An adhesion layer is formed over the 2D material layer. Source/drain electrodes are formed on opposite sides of the adhesion layer. A first high-k gate dielectric layer is formed over the adhesion layer, wherein the adhesion layer has a material different from a material of the first high-k gate dielectric layer.

A method of forming a complementary field-effect transistor (CFET) device includes: forming a plurality of channel regions stacked vertically over a fin; forming an isolation structure between a first subset of the plurality of channel regions and a second subset of the plurality of channel regions; forming a gate dielectric material around the plurality of channel regions and the isolation structure; forming a work function material around the gate dielectric material; forming a silicon-containing passivation layer around the work function material; after forming the silicon-containing passivation layer, removing a first portion of the silicon-containing passivation layer disposed around the first subset of the plurality of channel regions and keeping a second portion of the silicon-containing passivation layer disposed around the second subset of the plurality of channel regions; and after removing the first portion of the silicon-containing passivation layer, forming a gate fill material around the plurality of channel regions.

A method includes alternately stacking first semiconductor layers and second semiconductor layers over a substrate, patterning the first and second semiconductor layers into a fin structure, forming a dummy gate structure across the fin structure, depositing gate spacers over sidewalls of the dummy gate structure, removing the dummy gate structure to form a recess, removing the first semiconductor layers, depositing an interfacial layer wrapping the second semiconductor layers, depositing a high-k dielectric layer over the interfacial layer and over the sidewalls of the gate spacers, depositing a first gate electrode over the high-k dielectric layer, recessing the first gate electrode and the high-k dielectric layer to expose a top portion of the sidewalls of the gate spacers, depositing a low-k dielectric layer over the recessed high-k dielectric layer, and depositing a second gate electrode over the first gate electrode.

Semiconductor device and the manufacturing method thereof are disclosed. An exemplary method comprises forming a first stack structure and a second stack structure in a first area over a substrate, wherein each of the stack structures includes semiconductor layers separated and stacked up; depositing a first interfacial layer around each of the semiconductor layers of the stack structures; depositing a gate dielectric layer around the first interfacial layer; forming a dipole oxide layer around the gate dielectric layer; removing the dipole oxide layer around the gate dielectric layer of the second stack structure; performing an annealing process to form a dipole gate dielectric layer for the first stack structure and a non-dipole gate dielectric layer for the second stack structure; and depositing a first gate electrode around the dipole gate dielectric layer of the first stack structure and the non-dipole gate dielectric layer of the second stack structure.

A transistor with stable electrical characteristics. A semiconductor device includes a first insulator over a substrate, a second insulator over the first insulator, an oxide semiconductor in contact with at least part of a top surface of the second insulator, a third insulator in contact with at least part of a top surface of the oxide semiconductor, a first conductor and a second conductor electrically connected to the oxide semiconductor, a fourth insulator over the third insulator, a third conductor which is over the fourth insulator and at least part of which is between the first conductor and the second conductor, and a fifth insulator over the third conductor. The first insulator contains a halogen element.

A method includes: forming a sacrificial gate structure on the active region; forming a spacer structure including a first spacer, a second spacer, and an air-gap spacer, the air-gap spacer capped by bending an upper portion of the second spacer toward an upper portion of the first spacer; forming an insulating structure on the sides of the spacer structure; forming a gap region; and forming a gate structure including a gate dielectric layer, a gate electrode, and a gate capping layer in the gap region. The upper portion of the second spacer is in physical contact with the upper portion of the first spacer on a contact surface, and a lowermost end of the contact surface is on a level higher than an upper surface of the gate electrode with the substrate being a reference base level.

Disclosed are a semiconductor device and a method of fabricating the same. The device may include a substrate, an active pattern in an upper portion of the substrate and is extending in a first direction, a gate electrode crossing the active pattern and extending in a second direction intersecting the first direction, a first gate spacer covering a side surface of the gate electrode, a first inhibition layer between the gate electrode and the first gate spacer, and a gate insulating layer between the gate electrode and the active pattern. The gate insulating layer may include a high-k dielectric layer and a gate oxide layer. The gate oxide layer may be between the high-k dielectric layer and the active pattern. The high-k dielectric layer may be between the gate oxide layer and the gate electrode.