A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a substrate, a transistor, and a capacitor. The transistor includes a gate electrode disposed on the substrate. The capacitor is electrically connected to the transistor and includes a capacitor dielectric and a capacitor electrode. The capacitor dielectric and the capacitor electrode are stacked over the gate electrode of the transistor.

A semiconductor device includes a sensing element including a sensing electrode and a filter covering the sensing electrode. The filter includes a first work function layer and a second work function layer. The first work function layer is over the sensing electrode. The second work function layer is over the first work function layer. A work function value of the second work function layer is greater than a work function value of the first work function layer, and an atomic percentage of metal in the second work function layer is greater than an atomic percentage of metal in the first work function layer.

Exemplary semiconductor structures and processing methods may include forming a first portion of a first semiconductor layer characterized by a first etch rate for an etch treatment, forming a second portion of the first semiconductor layer characterized by a second etch rate that is less than the first etch rate for the etch treatment, and forming a third portion of the first semiconductor layer characterized by a third etch rate that is greater than the second etch rate. The processing methods may further include etching an opening through the first semiconductor layer, where the opening has a height and a width, and where the opening is characterized by a variation in the width between a midpoint of the height of the opening and an endpoint of the opening that is less than or about 5 .

Methods for forming semiconductor structures are provided. The method for forming the semiconductor structure includes forming a word line cell over a substrate and forming a dielectric layer over the word line cell. The method further includes forming a conductive layer over the dielectric layer and polishing the conductive layer until the dielectric layer is exposed. The method further includes forming an oxide layer on a top surface of the conductive layer and removing portions of the conductive layer not covered by the oxide layer to form a memory gate.

According to one embodiment, a non-volatile semiconductor memory device includes: a tunnel insulation film provided on a semiconductor substrate; a floating gate electrode provided on the tunnel insulation film; an inter-electrode insulation film provided on the floating gate electrode; and a control gate electrode provided on the inter-electrode insulation film. The inter-electrode insulation film includes: a lower insulation film provided on the floating gate electrode side; and an upper insulation film provided on the control gate electrode side. The lower insulation film includes: N (N is an integer of 2 or larger) electric charge accumulation layers; and boundary insulation films provided between the electric charge accumulation layers.

A method for fabricating memory device includes the steps of: providing a substrate; forming a tunnel oxide layer on the substrate; forming a first gate layer on the tunnel oxide layer; forming a negative capacitance (NC) insulating layer on the first gate layer; and forming a second gate layer on the NC insulating layer. Preferably, the second gate layer further includes a work function metal layer on the NC insulating layer and a low resistance metal layer on the work function metal layer.

Semiconductor memory having both volatile and non-volatile modes and methods of operation. A semiconductor storage device includes a plurality of memory cells each having a floating body for storing, reading and writing data as volatile memory. The device includes a floating gate or trapping layer for storing data as non-volatile memory, the device operating as volatile memory when power is applied to the device, and the device storing data from the volatile memory as non-volatile memory when power to the device is interrupted.

A method includes forming a first material stack above a first transistor region, a second transistor region, and a dummy gate region of a semiconductor structure, the first material stack including a high-k material layer and a workfunction adjustment metal layer. The first material stack is patterned to remove a first portion of the first material stack from above the dummy gate region while leaving second portions of the first material stack above the first and second transistor regions. A gate electrode stack is formed above the first and second transistor regions and above the dummy gate region, and the gate electrode stack and the remaining second portions of the first material stack are patterned to form a first gate structure above the first transistor region, a second gate structure above the second transistor region, and a dummy gate structure above the dummy gate region.

A method of making a monolithic three dimensional NAND string is provided. A stack of alternating layers of a first material and a second material different from the first material is formed over a substrate. The stack is etched to form at least one opening in the stack. A charge storage material layer is formed on a sidewall of the at least one opening. A tunnel dielectric layer is formed on the charge storage material layer in the at least one opening. A semiconductor channel material is formed on the tunnel dielectric layer in the at least one opening. The first material layers are selectively removed to expose side wall of the charge storage material layer. A blocking dielectric is formed on the exposed side wall of the charge storage material layer. Control gates are formed on the blocking dielectric.

A flash memory cell structure includes a semiconductor substrate, a pad dielectric layer, a floating gate, a control gate, and a blocking layer. The pad dielectric layer is disposed on the semiconductor substrate. The floating gate is disposed over the pad dielectric layer, in which the floating gate has a top surface opposite to the pad dielectric layer, and the top surface includes at least one recess formed thereon. The control gate is disposed over the top surface of the floating gate. The blocking layer is disposed between the floating gate and the control gate.