A method comprises forming a first insulation layer on an upper surface of a semiconductor substrate, forming a first conductive layer on the first insulation layer, and forming a compound insulation layer on the first conductive layer, wherein the compound insulation layer comprises a nitride sublayer between a lower oxide sublayer and an upper oxide sublayer. A second insulation layer is formed on the compound insulation layer. A trench is formed that extends through the second insulation layer, the compound insulation layer, the first conductive layer, the first insulation layer, and into the semiconductor substrate. The trench is filled with fill insulation material. The second insulation layer and an upper portion of the fill insulation material are removed. A second conductive layer is formed on the compound insulation layer, and on the fill insulation material in the trench.

Disclosed are memory structures and methods for forming such structures. An example method forms a vertical string of memory cells by forming an opening in interleaved tiers of dielectric tier material and nitride tier material, forming a charge storage material over sidewalls of the opening and recesses in the opening to form respective charge storage structures within the recesses. Subsequently, and separate from the formation of the floating gate structures, at least a portion of the remaining nitride tier material is removed to produce control gate recesses, each adjacent a respective charge storage structure. A control gate is formed in each control gate recess, and the control gate is separated from the charge storage structure by a dielectric structure. In some examples, these dielectric structures are also formed separately from the charge storage structures.

A semiconductor device includes a semiconductor substrate having an upper surface with a semiconductor member extending vertically from the upper surface, wherein the semiconductor member has a first conductivity type. A first region of a second conductivity type different than the first conductivity type is formed at a proximal end of the semiconductor member adjacent the upper surface. A second region of the second conductivity type is formed at a distal end of the semiconductor member. A channel region of the semiconductor member extends between the first and second regions. A floating gate laterally wraps around a first portion of the channel region. A control gate laterally wraps around the floating gate. A select gate laterally wraps around a second portion of the channel region. An erase gate laterally wraps around the semiconductor member.

Various embodiments of the present disclosure are directed towards a method for opening a source line in a memory device. An erase gate line (EGL) and the source line are formed elongated in parallel. The source line underlies the EGL and is separated from the EGL by a dielectric layer. A first etch is performed to form a first opening through the EGL and stops on the dielectric layer. A second etch is performed to thin the dielectric layer at the first opening, wherein the first and second etches are performed with a common mask in place. A silicide process is performed to form a silicide layer on the source line at the first opening, wherein the silicide process comprises a third etch with a second mask in place and extends the first opening through the dielectric layer. A via is formed extending through the EGL to the silicide layer.

A flash memory device includes a floating gate electrode formed within a substrate semiconductor layer having a doping of a first conductivity type, a pair of active regions formed within the substrate semiconductor layer, having a doping of a second conductivity type, and laterally spaced apart by the floating gate electrode, an erase gate electrode formed within the substrate semiconductor layer and laterally offset from the floating gate electrode, and a control gate electrode that overlies the floating gate electrode. The floating gate electrode may be formed in a first opening in the substrate semiconductor layer, and the erase gate electrode may be formed in a second opening in the substrate semiconductor layer. Multiple instances of the flash memory device may be arranged as a two-dimensional array of flash memory cells.

Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a memory cell included in a memory cell string; the memory cell including charge storage structure and channel structure separated from the charge storage structure by a dielectric structure; a first control gate associated with the memory cell and located on a first side of the charge storage structure and a first side of the channel structure; and a second control gate associated with the memory cell and electrically separated from the first control gate, the second control gate located on a second side of the charge storage structure and a second side of the channel structure.

In a method of manufacturing a semiconductor device, a memory cell structure covered by a protective layer is formed in a memory cell area of a substrate. A mask pattern is formed. The mask pattern has an opening over a first circuit area, while the memory cell area and a second circuit area are covered by the mask pattern. The substrate in the first circuit area is recessed, while the memory cell area and the second circuit area are protected. A first field effect transistor (FET) having a first gate dielectric layer is formed in the first circuit area over the recessed substrate and a second FET having a second gate dielectric layer is formed in the second circuit area over the substrate as viewed in cross section.

A memory structure including a substrate, charge storage layers, and a gate is provided. The charge storage layers are located on the substrate. The gate is located on the substrate on one side of the charge storage layers. The gate extends along a first direction. The gate has a protruding portion protruding along a second direction. The second direction intersects the first direction. The protruding portion is located between two adjacent charge storage layers arranged along the first direction.

A semiconductor device including a memory cell featuring a first gate insulating film over a semiconductor substrate, a control gate electrode over the first gate insulating film, a second gate insulating film over the substrate and a side wall of the control gate electrode, a memory gate electrode over the second gate insulating film arranged adjacent with the control gate electrode through the second gate insulating film, first and second semiconductor regions in the substrate positioned on a control gate electrode side and a memory gate side, respectively, the second gate insulating film featuring a first film over the substrate, a charge storage film over the first film and a third film over the second film, the first film having a first portion between the substrate and memory gate electrode and a thickness greater than that of a second portion between the control gate electrode and the memory gate electrode.

A method of forming split gate non-volatile memory cells on the same chip as logic and high voltage devices having HKMG logic gates. The method includes forming the source and drain regions, floating gates, control gates, and the poly layer for the erase gates and word line gates in the memory area of the chip. A protective insulation layer is formed over the memory area, and an HKMG layer and poly layer are formed on the chip, removed from the memory area, and patterned in the logic areas of the chip to form the logic gates having varying amounts of underlying insulation.