There is provided a semiconductor device including: a semiconductor substrate; a gate insulating film provided on the semiconductor substrate; a gate electrode layer that is provided on the gate insulating film and contains impurity ions; and source or drain regions that are provided on the semiconductor substrate on both sides of the gate electrode layer and contain conductive impurities, in which a concentration of the impurity ions in the gate electrode layer is higher than concentrations of the conductive impurities in the source or drain regions.

A semiconductor process is described. A silicon-phosphorus (SiP) epitaxial layer is formed serving as a source/drain (S/D) region. A crystalline metal silicide layer is formed directly on the SiP epitaxial layer and thus prevents oxidation of the SiP epitaxial layer. A contact plug is formed over the crystalline metal silicide layer.

A semiconductor device includes: a sidewall insulating film; a gate electrode; source and drain regions; a first stress film; and a second stress film.

Embodiments of the present invention provide a structure and method of minimizing stress relaxation during fin formation. Embodiments may involve forming a looped spacer on an upper surface of a substrate and adjacent to at least a sidewall of a mandrel. The mandrel may be removed, leaving the looped spacer on the substrate. An exposed portion of the substrate may be removed to form a looped fin below the looped spacer. The spacer may be removed, leaving a looped fin. A looped fin formation may reduce stress relaxation compared to conventional fin formation methods. Embodiments may include forming a gate over a looped portion of a looped fin. Securing a looped portion in position with a gate may decrease stress relaxation in the fin. Thus, a looped fin with a looped portion of the looped fin under a gate may have substantially reduced stress relaxation compared to a conventional fin.

A semiconductor device includes first and second fins on first and second regions of a substrate, a first trench overlapping a vertical end portion of the first fin and including first upper and lower portions, the first upper and lower portions separated by an upper surface of the first fin, a second trench overlapping a vertical end portion of the second fin and including second upper and lower portions separated by an upper surface of the second fin, a first dummy gate electrode including first metal oxide and filling layers, the first metal oxide layer filling the first lower portion of the first trench and is along a sidewall of the first upper portion of the first trench, and a second dummy gate electrode filling the second trench and including second metal oxide and filling layers, the second metal oxide layer extending along sidewalls of the second trench.

A semiconductor process is described. A silicon-phosphorus (SiP) epitaxial layer is formed serving as a source/drain (S/D) region. A crystalline metal silicide layer is formed directly on the SiP epitaxial layer and thus prevents oxidation of the SiP epitaxial layer. A contact plug is formed over the crystalline metal silicide layer.

A method for fabricating a semiconductor device comprises forming a replacement gate structure on a semiconductor layer of a substrate. The replacement gate structure at least including a polysilicon layer. After forming the replacement gate structure, a gate spacer is formed on the replacement gate structure. Atoms are implanted in an upper portion of the polysilicon layer. The implanting expands the upper portion of the polysilicon layer and a corresponding upper portion of the gate spacer in at least a lateral direction beyond a lower portion of the polysilicon layer and a lower portion of the spacer, respectively. After the atoms have been implanted, the polysilicon layer is removed to form a gate cavity. A metal gate stack is formed within the gate cavity. The metal gate stack includes an upper portion having a width that is greater than a width of a lower portion of the metal gate stack.

Embodiments of the present invention provide a structure and method of minimizing stress relaxation during fin formation. Embodiments may involve forming a looped spacer on an upper surface of a substrate and adjacent to at least a sidewall of a mandrel. The mandrel may be removed, leaving the looped spacer on the substrate. An exposed portion of the substrate may be removed to form a looped fin below the looped spacer. The spacer may be removed, leaving a looped fin. A looped fin formation may reduce stress relaxation compared to conventional fin formation methods. Embodiments may include forming a gate over a looped portion of a looped fin. Securing a looped portion in position with a gate may decrease stress relaxation in the fin. Thus, a looped fin with a looped portion of the looped fin under a gate may have substantially reduced stress relaxation compared to a conventional fin.

A semiconductor device is provided that includes a gate structure on a channel region of a substrate. A source region and a drain region are present on opposing sides of the channel region. A first metal semiconductor alloy is present on an upper surface of at least one of the source and drain regions. The first metal semiconductor alloy extends to a sidewall of the gate structure. A dielectric layer is present over the gate structure and the first metal semiconductor alloy. An opening is present through the dielectric layer to a portion of the first metal semiconductor alloy that is separated from the gate structure. A second metal semiconductor alloy is present in the opening, is in direct contact with the first metal semiconductor alloy, and has an upper surface that is vertically offset and is located above the upper surface of the first metal semiconductor alloy.

A semiconductor device includes a gate structure disposed over a substrate, and sidewall spacers disposed on both side walls of the gate structure. The sidewall spacers includes at least four spacer layers including first to fourth spacer layers stacked in this order from the gate structure.