A substrate includes a support structure comprising a polycrystalline ceramic core, a first adhesion layer encapsulating the polycrystalline ceramic core, a barrier layer encapsulating the first adhesion layer, a second adhesion layer coupled to the barrier layer, and a conductive layer coupled to the second adhesion layer. The substrate also includes a bonding layer coupled to the support structure, a substantially single crystal silicon layer coupled to the bonding layer, and an epitaxial semiconductor layer coupled to the substantially single crystal silicon layer.

A III-N semiconductor channel is formed on a III-N transition layer formed on a (111) or (110) surface of a silicon template structure, such as a fin sidewall. In embodiments, the silicon fin has a width comparable to the III-N epitaxial film thicknesses for a more compliant seeding layer, permitting lower defect density and/or reduced epitaxial film thickness. In embodiments, a transition layer is GaN and the semiconductor channel comprises Indium (In) to increase a conduction band offset from the silicon fin. In other embodiments, the fin is sacrificial and either removed or oxidized, or otherwise converted into a dielectric structure during transistor fabrication. In certain embodiments employing a sacrificial fin, the III-N transition layer and semiconductor channel is substantially pure GaN, permitting a breakdown voltage higher than would be sustainable in the presence of the silicon fin.

A junction field effect transistor (JFET) comprises an insulating carrier substrate, a base semiconductor substrate formed on the insulating carrier substrate and a gate region formed on the base semiconductor substrate. The gate region forms a junction with the base semiconductor substrate. The JFET further comprises a first source/drain region formed on the base semiconductor substrate and located on a first side of the gate region and a second source/drain region formed on the base semiconductor substrate and located on a second side of the gate region. A gate stack is deposited on the gate region, a first source/drain stack is deposited on the first source/drain region and a second source/drain stack is deposited on the second source/drain region. At least one of the gate stack, first source/drain stack and second source/drain stack overlaps onto another one of the gate stack, first source/drain stack and second source/drain stack.

A junction field effect transistor (JFET) comprises an insulating carrier substrate, a base semiconductor substrate formed on the insulating carrier substrate and a gate region formed on the base semiconductor substrate. The gate region forms a junction with the base semiconductor substrate. The JFET further comprises a first source/drain region formed on the base semiconductor substrate and located on a first side of the gate region and a second source/drain region formed on the base semiconductor substrate and located on a second side of the gate region. A gate stack is deposited on the gate region, a first source/drain stack is deposited on the first source/drain region and a second source/drain stack is deposited on the second source/drain region. At least one of the gate stack, first source/drain stack and second source/drain stack overlaps onto another one of the gate stack, first source/drain stack and second source/drain stack.

A III-N semiconductor channel is formed on a III-N transition layer formed on a (111) or (110) surface of a silicon template structure, such as a fin sidewall. In embodiments, the silicon fin has a width comparable to the III-N epitaxial film thicknesses for a more compliant seeding layer, permitting lower defect density and/or reduced epitaxial film thickness. In embodiments, a transition layer is GaN and the semiconductor channel comprises Indium (In) to increase a conduction band offset from the silicon fin. In other embodiments, the fin is sacrificial and either removed or oxidized, or otherwise converted into a dielectric structure during transistor fabrication. In certain embodiments employing a sacrificial fin, the III-N transition layer and semiconductor channel is substantially pure GaN, permitting a breakdown voltage higher than would be sustainable in the presence of the silicon fin.

A junction field effect transistor (JFET) comprises an insulating carrier substrate, a base semiconductor substrate formed on the insulating carrier substrate and a gate region formed on the base semiconductor substrate. The gate region forms a junction with the base semiconductor substrate. The JFET further comprises a first source/drain region formed on the base semiconductor substrate and located on a first side of the gate region and a second source/drain region formed on the base semiconductor substrate and located on a second side of the gate region. A gate stack is deposited on the gate region, a first source/drain stack is deposited on the first source/drain region and a second source/drain stack is deposited on the second source/drain region. At least one of the gate stack, first source/drain stack and second source/drain stack overlaps onto another one of the gate stack, first source/drain stack and second source/drain stack.

A semiconductor device includes: a substrate; a nitride semiconductor layer on the substrate; a source electrode, a drain electrode and a gate electrode on the nitride semiconductor layer; and a SiN surface protective film covering the nitride semiconductor layer, wherein a composition ratio Si/N of Si and N that form a SiN bond of the SiN surface protective film is 0.751 to 0.801

A junction field-effect transistor (JFET) with a gate region that includes two separate sub-regions having material of different conductivity types and/or a Schottky junction that substantially suppresses gate current when the gate junction is forward-biased, as well as complementary circuits that incorporate such JFET devices.

Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a semiconductor substrate and a fin structure over the semiconductor substrate. The semiconductor device structure also includes a gate stack over a portion of the fin structure, and the fin structure includes an intermediate portion under the gate stack and upper portions besides the intermediate portion. The semiconductor device structure further includes a contact layer over the fin structure. The contact layer includes a metal material, and the upper portions of the fin structure also include the metal material.

A method of manufacturing a substrate includes forming a support structure by providing a polycrystalline ceramic core, forming a first adhesion layer coupled to the polycrystalline ceramic core, forming a conductive layer coupled to the first adhesion layer, forming a second adhesion layer coupled to the conductive layer, and forming a barrier layer coupled to the second adhesion layer. The method also includes forming a bonding layer coupled to the support structure, joining a substantially single crystal layer to the bonding layer, wherein the substantially single crystal layer comprises at least one of silicon carbide, sapphire, or gallium nitride, and forming one or more epitaxial III-V layers coupled to the substantially single crystal layer.