A semiconductor film, a sheet like object, and a semiconductor device are provided that have inhibited semiconductor properties, particularly leakage current, and excellent withstand voltage and heat dissipation. A crystalline semiconductor film or a sheet like object includes a corundum structured oxide semiconductor as a major component, wherein the film has a film thickness of 1 m or more. Particularly, the semiconductor film or the object includes a semiconductor component of oxide of one or more selected from gallium, indium, and aluminum as a major component. A semiconductor device has a semiconductor structure including the semiconductor film or the object.

According to one embodiment, an apparatus includes a substrate, and at least one three dimensional (3D) structure above the substrate. The substrate and the 3D structure each include a semiconductor material. The 3D structure also includes: a first region having a first conductivity type, and a second region coupled to a portion of at least one vertical sidewall of the 3D structure.

The present invention discloses an electronic device using a group III nitride substrate fabricated via the ammonothermal method. By utilizing the high-electron concentration of ammonothermally grown substrates having the dislocation density less than 10.sup.5 cm.sup.2, combined with a high-purity active layer of Ga.sub.1-x-yAl.sub.xIn.sub.yN (0x1, 0y1) grown by a vapor phase method, the device can attain high level of breakdown voltage as well as low on-resistance. To realize a good matching between the ammonothermally grown substrate and the high-purity active layer, a transition layer is optionally introduced. The active layer is thicker than a depletion region created by a device structure in the active layer.

A vertical JFET with a ladder termination may be made by a method using a limited number of masks. A first mask is used to form mesas and trenches in active cell and termination regions simultaneously. A mask-less self-aligned process is used to form silicide source and gate contacts. A second mask is used to open windows to the contacts. A third mask is used to pattern overlay metallization. An optional fourth mask is used to pattern passivation. Optionally the channel may be doped via angled implantation, and the width of the trenches and mesas in the active cell region may be varied from those in the termination region.

A method for forming a field-effect semiconductor device includes: providing a wafer having a main surface and a first semiconductor layer of a first conductivity type; forming at least two trenches from the main surface partly into the first semiconductor layer so that each of the at least two trenches includes, in a vertical cross-section substantially orthogonal to the main surface, a side wall and a bottom wall, and that a semiconductor mesa is formed between the side walls of the at least two trenches; forming at least two second semiconductor regions of a second conductivity type in the first semiconductor layer so that the bottom wall of each of the at least two trenches adjoins one of the at least two second semiconductor regions; and forming a rectifying junction at the side wall of at least one of the at least two trenches.

A nitride semiconductor device includes: a substrate; a nitride semiconductor layer above the substrate; a high-resistance layer above the nitride semiconductor layer; a p-type nitride semiconductor layer above the high-resistance layer; a first opening penetrating through the p-type nitride semiconductor layer and the high-resistance layer to the nitride semiconductor layer; an electron transport layer and an electron supply layer covering an upper portion of the p-type nitride semiconductor layer and the first opening; a gate electrode above the electron supply layer; a source electrode in contact with the electron supply layer; a second opening penetrating through the electron supply layer and the electron transport layer to the p-type nitride semiconductor layer; a potential fixing electrode in contact with the p-type nitride semiconductor layer at a bottom part of the second opening; and a drain electrode.

The present application provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes: a first n-type semiconductor layer, a p-type semiconductor layer, and a second n-type semiconductor layer which are stacked. A buried layer made of AlGaN is disposed in the first n-type semiconductor layer. A trench at least penetrates through the second n-type semiconductor layer and the p-type semiconductor layer. At least part of the buried layer is reserved below the trench. A gate electrode is in the trench. The method is used to manufacture this semiconductor structure.

A semiconductor device includes a first conductive part, a second conductive part, a third conductive part, a first insulating part, and a semiconductor part of a first conductivity type. The second conductive part is separated from the first conductive part in a first direction. The third conductive part arranged with a portion of the second conductive part in a second direction crossing the first direction. The first insulating part includes a first insulating region located between the third conductive part and the portion of the second conductive part. The semiconductor part includes a first semiconductor region and a second semiconductor region. The first semiconductor region is located between the first conductive part and the second conductive part. The second semiconductor region is located between the first insulating region and the portion of the second conductive part. The second semiconductor region has a Schottky junction with the second conductive part.

The major element includes a first electrode, a second electrode, a first semiconductor layer located between the first electrode and the second electrode, the first semiconductor layer forming a first Schottky junction with the second electrode, and a first gate electrode facing the first Schottky junction. The control element includes a third electrode, a fourth electrode, a second semiconductor layer located between the third electrode and the fourth electrode, the second semiconductor layer forming a second Schottky junction with the fourth electrode, and a second gate electrode facing the second Schottky junction.

A nitride semiconductor device includes: a substrate; a drift layer, a high-resistance layer, and a first base layer above the substrate in stated order; a gate opening penetrating through the first base layer and the high-resistance layer to the drift layer; an electron transport layer and an electron supply layer covering an upper portion of the first base layer and the gate opening; a gate electrode above the electron supply layer; a source electrode in contact with the electron supply layer; an electrode opening penetrating through the electron supply layer and the electron transport layer to the first base layer; a potential fixing electrode in contact with the first base layer at a bottom part of the electrode opening; and a drain electrode below the substrate.