A display device includes a pixel including a first sub-pixel emitting light of a first color and a second sub-pixel emitting light of a second color. Each of the first sub-pixel and the second sub-pixel includes: a pixel circuit layer disposed on a substrate, the pixel circuit layer including a pixel circuit, and a display element layer disposed on the pixel circuit layer, the display element layer including a light emitting element which includes an anode electrode and a cathode electrode. The pixel circuit layer includes a first contact part disposed between the substrate and the display element layer, the anode electrode and the pixel circuit being connected to each other through the first contact part to supply an anode signal to the light emitting element. A plurality of first contact parts which include a first contact part in the first sub-pixel and a first contact part in the second sub-pixel are arranged along a first direction.

A display device includes a first electrode and a second electrode which are spaced apart from each other on a substrate. A light emitting element is disposed between the first electrode and the second electrode. A light emitting element core of the light emitting element includes a first semiconductor layer, a second semiconductor layer spaced apart from the first semiconductor layer, and a light emitting layer disposed between the first semiconductor layer and the second semiconductor layer. A first element insulating layer surrounds a side surface of the light emitting element core. The first element insulating layer is an oxide insulating layer having a single crystalline structure.

In accordance with aspects of the present technology, a unique charge carrier transfer process from c-plane InGaN to semipolar-plane InGaN formed spontaneously in nanowire heterostructures can effectively reduce the instantaneous charge carrier density in the active region, thereby leading to significantly enhanced emission efficiency in the deep red wavelength. Furthermore, the total built-in electric field can be reduced to a few kV/cm by cancelling the piezoelectric polarization with spontaneous polarization in strain-relaxed high indium composition InGaN/GaN heterostructures. An ultra-stable red emission color can be achieved in InGaN over four orders of magnitude of excitation power range. Accordingly, aspects of the present technology advantageously provide a method for addressing some of the fundamental issues in light-emitting devices and advantageously enables the design of high efficiency and high stability optoelectronic devices.

A transistor having at least one passivated Schottky barrier to a channel includes an insulated gate structure on a p-type substrate in which the channel is located beneath the insulated gate structure. The channel and the insulated gate structure define a first and second undercut void regions that extend underneath the insulated gate structure toward the channel from a first and a second side of the insulated gate structure, respectively. A passivation layer is included on at least one exposed sidewall surface of the channel and metal source and drain terminals are located on respective first and second sides of the channel, including on the passivation layer and within the undercut void regions beneath the insulated gate structure. At least one of the metal source and drain terminals comprises a metal that has a work function near a valence band of the p-type substrate.

A junction field-effect transistor (JFET) with a gate region that includes two separate sub-regions having material of different conductivity types and/or a Schottky junction that substantially suppresses gate current when the gate junction is forward-biased, as well as complementary circuits that incorporate such JFET devices.

A transistor having at least one passivated Schottky barrier to a channel includes an insulated gate structure on a p-type substrate in which the channel is located beneath the insulated gate structure. The channel and the insulated gate structure define a first and second undercut void regions that extend underneath the insulated gate structure toward the channel from a first and a second side of the insulated gate structure, respectively. A passivation layer is included on at least one exposed sidewall surface of the channel and metal source and drain terminals are located on respective first and second sides of the channel, including on the passivation layer and within the undercut void regions beneath the insulated gate structure. At least one of the metal source and drain terminals comprises a metal that has a work function near a valence band of the p-type substrate.

A junction field-effect transistor (JFET) with a gate region that includes two separate sub-regions having material of different conductivity types and/or a Schottky junction that substantially suppresses gate current when the gate junction is forward-biased, as well as complementary circuits that incorporate such JFET devices.