The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; a valley inwardly positioned on a top surface of the substrate; a programmable insulating layer conformally positioned on the valley and including a V-shaped cross-sectional profile; and a top electrode positioned on the programmable insulating layer. The programmable insulating layer is configured to be blown out under a programming voltage.

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; a valley inwardly positioned on a top surface of the substrate; a programmable insulating layer conformally positioned on the valley and including a V-shaped cross-sectional profile; and a top electrode positioned on the programmable insulating layer. The programmable insulating layer is configured to be blown out under a programming voltage.

A semiconductor structure includes a substrate and a capacitor over the substrate. The capacitor includes a silicide layer over the substrate. The capacitor includes a first dielectric layer over the silicide layer. The capacitor includes a metal gate structure over the first dielectric layer, where a top portion of the metal gate structure is over the substrate and a bottom portion of the metal gate structure extends into the substrate. The capacitor includes a second dielectric layer over the metal gate structure. The capacitor further includes a conductive structure over the second dielectric layer.

Semiconductor devices are described that include a capacitor integrated therein. In an implementation, the semiconductor devices include a substrate. The substrate includes multiple capacitor regions, such as a first capacitor region and a second capacitor region that are adjacent to one another. Each capacitor region includes trenches that are formed within the substrate. A metal-insulator-metal capacitor is formed within the trenches and at least partially over the substrate. The trenches disposed within the first capacitor region are at least substantially perpendicular to the trenches disposed within the second capacitor region.

A semiconductor device having first and second conductivity regimes is provided. The device comprises a substrate body, a source formed along a first sidewall of the substrate body, and a drain formed along a second sidewall of the substrate body. The device comprises first and second delta layers disposed on the substrate body and separated by a gap. The first delta layer is in contact with the source and the second delta layer is in contact with the drain. The device comprises a cap disposed over the first and second delta layers. The device has the first conductivity regime responsive to a first voltage between the drain and the source and has the second conductivity regime responsive to a second voltage between the drain and the source.

A ferroelectric tunnel junction (FTJ) memory device may include a first electrode and a ferroelectric layer comprising ferroelectric dipoles that may generate a first electric field. The first electric field may be oriented in a first direction when the device operates in an ON state. The device may also include a barrier layer that may generate a depolarizing second electric field that may be oriented in a second direction opposite of the first direction when the device operates in the ON state. The device may further include a second electrode. The first electrode and the second electrode may generate a third electric field that is oriented in the first direction when the device operates in the ON state.

A semiconductor device includes a first and a second switching element, a first and a second conductive member, and a capacitor. The first switching element has a first element obverse surface and a first element reverse surface facing away from each other in a first direction. The second switching element has a second element obverse surface and a second element reverse surface facing away from each other in the first direction. The first and second conductive members are spaced apart in a second direction orthogonal to the first direction. The capacitor has a first and a second connection terminal. The first and second switching elements are connected in series, forming a bridge. The first and second connection terminals are electrically connected to opposite ends of the bridge. The capacitor and the first switching element are on the first conductive member, the second switching element on the second conductive member.

A semiconductor device includes a semiconductor substrate. The semiconductor device further includes a doped well disposed over the semiconductor substrate and including a first dopant having a conductivity type different than a conductivity type of the semiconductor device. The semiconductor device further includes a first doped layer disposed within the doped well and including a second dopant having the conductivity type of the semiconductor device. The semiconductor device further includes a source region and a drain region disposed within the first doped layer. The semiconductor device further includes an isolation structure disposed adjacent to the first doped layer. The semiconductor device further includes a second doped layer disposed adjacent to the isolation structure and over the doped well. In some aspects, the second doped layer includes a third dopant having a conductivity type different than the conductivity type of the semiconductor device.

An object is to provide a technique that ensures to reduce a parasitic resistance of a semiconductor device while enhancing a breakdown voltage property of a semiconductor device. A portion of a second semiconductor layer exposed from a first semiconductor layer corresponds to a concave portion of a laminated structure and the first semiconductor layer or an adjacent portion of the first semiconductor layer and a second semiconductor layer corresponds to a convex portion of the laminated structure. A first guard ring of a second conductivity type is arranged on side walls of the convex portion, and in the concave portion, a guard ring of the second conductivity type is not arranged, or a second guard ring of the second conductivity type having a thickness thinner than that of the first guard ring is arranged.

A capacitor includes a silicon substrate, a dielectric layer, and a conductor layer. The silicon substrate has a doped layer. The doped layer includes a first doped layer disposed along a second region of a first principal surface of the silicon substrate, a second doped layer disposed at a bottom part of the porous part of the silicon substrate, and a third doped layer disposed at a side part of the porous part of the silicon substrate. The doped layer includes a first portion connecting the first doped layer to the third doped layer and having a first curved part concavely curved in a cross-sectional view. The doped layer includes a second portion connecting the second doped layer to the third doped layer and having a second curved part convexly curved in the cross-sectional view.