A method for manufacturing a semiconductor structure includes: providing a base having first contact layers and a second contact layer; forming an initial electrical connection layer; forming a lower mask layer including a first and a second pattern regions, and on an upper surface of the base, orthographic projections of two first contact layers fall within an orthographic projection of one first pattern region, and an orthographic projection of one second contact layer falls within an orthographic projection of one second pattern region; patterning the first pattern region to form two first sub-pattern regions discrete from each other; and etching the initial electrical connection layer to form first electrical connection layers and a second electrical connection layer discrete from each other, in which the first electrical connection layers correspond to the first sub-pattern regions, and the second electrical connection layer corresponds to the second pattern region.

A superlattice cell that includes Group IV elements is repeated multiple times so as to form the superlattice. Each superlattice cell has multiple ordered atomic planes that are parallel to one another. At least two of the atomic planes in the superlattice cell have different chemical compositions. One or more of the atomic planes in the superlattice cell one or more components selected from the group consisting of carbon, tin, and lead. These superlattices make a variety of applications including, but not limited to, transistors, light sensors, and light sources.

A semiconductor device includes a first load terminal, a second load terminal and a semiconductor body coupled to the first load terminal and the second load terminal. The semiconductor body is configured to conduct a load current along a load current path between the first load terminal and the second load terminal. The semiconductor device further includes a control electrode electrically insulated from the semiconductor body and configured to control a part of the load current path, and an electrically floating sensor electrode arranged adjacent to the control electrode. The sensor electrode is electrically insulated from each of the semiconductor body, and the control electrode and is capacitively coupled to the load current path.

A superlattice cell that includes Group IV elements is repeated multiple times so as to form the superlattice. Each superlattice cell has multiple ordered atomic planes that are parallel to one another. At least two of the atomic planes in the superlattice cell have different chemical compositions. One or more of the atomic planes in the superlattice cell one or more components selected from the group consisting of carbon, tin, and lead. These superlattices make a variety of applications including, but not limited to, transistors, light sensors, and light sources.

The present invention generally relates to nanoscale wires, and to systems and methods of producing nanoscale wires. In some aspects, the present invention is generally related to facet-specific deposition on semiconductor surfaces. In one embodiment, a first surface of a nanoscale wire, or a semiconductor, is preferentially oxidized relative to a second surface, and material is preferentially deposited on the second surface relative to the first surface. For example, the nanoscale wire or semiconductor may be a silicon nanowire that is initially exposed to an etchant to remove silicon oxide, then exposed to an oxidant under conditions such that one facet or surface (e.g., a {113} facet) is oxidized more quickly than another facet or surface (e.g., a {111} facet). Material may then be deposited or immobilized on the less-oxidized facet relative to the more-oxidized facet. Other embodiments of the invention may be directed to articles made thereby, devices containing such nanoscale wires or semiconductors, kits involving such nanoscale wires or semiconductors, semiconductor surfaces, or the like.

A superlattice cell that includes Group IV elements is repeated multiple times so as to form the superlattice. Each superlattice cell has multiple ordered atomic planes that are parallel to one another. At least two of the atomic planes in the superlattice cell have different chemical compositions. One or more of the atomic planes in the superlattice cell one or more components selected from the group consisting of carbon, tin, and lead. These superlattices make a variety of applications including, but not limited to, transistors, light sensors, and light sources.

A spin valve element 10 including a spin injector 12 made of a ferromagnetic material, a spin detector 16 made of a ferromagnetic material, and a channel part 14 made of a non-magnetic material. The spin detector 16 is arranged at a position separated from the spin injector 12, the channel part 14 is connected with the spin injector 12 and the spin detector 16 directly or through an insulating layer, and a plurality of spin diffusion portions 30 to 34 with enlarged cross section areas in a direction perpendicular to a spin current is formed in the channel part 14.

A two-terminal memory device includes: a substrate; an extended drain extending from a drain and a lower surface of the drain and laminated on the substrate; a ferroelectric layer connected to the drain and covering the extended drain and the substrate; and a source laminated on the ferroelectric layer to face the drain.

A method for manufacturing a two-terminal memory device includes: forming an extended drain and a drain layer on a substrate; forming a ferroelectric layer covering the substrate and the extended drain; forming a semiconducting layer on the ferroelectric layer, and forming a source layer connected to the semiconducting layer on the ferroelectric layer.

A multilayer stacking wafer bonding structure is provided in the present invention, including a logic wafer with a substrate and a logic circuit layer on the substrate, multiple memory wafers bonded sequentially on the logic circuit layer to form a first multilayer stacking structure, wherein each memory wafer includes a memory layer, a silicon layer on the memory layer and multiple oxide layers in trenches of the silicon layer, and the oxide layers in the memory wafers are aligned each other in a direction vertical to the substrate, and multiple through-oxide vias (TOV) extending through the memory layers and the oxide layers in the first multilayer stacking structure into the logic circuit layer, and the TOVs do not extend through any of the silicon layers.