A device includes a substrate, a heterostructure supported by the substrate, the heterostructure including a semiconductor layer supported by the substrate, and a ferroelectric III-nitride alloy layer supported by the semiconductor layer, the ferroelectric III-nitride alloy layer including a Group IIIB element, and first and second contacts in electrical communication with the ferroelectric III-nitride alloy layer and the semiconductor layer, respectively, such that a polarity of a poling voltage applied across the first and second contacts establishes a state of ferroelectric polarization of the ferroelectric III-nitride alloy layer

Quantum dot devices and related methods and systems that use semiconductor nanoribbons arranged in a grid where a plurality of first nanoribbons, substantially parallel to one another, intersect a plurality of second nanoribbons, also substantially parallel to one another but at an angle with respect to the first nanoribbons, are disclosed. Different gates at least partially wrap around individual portions of the first and second nanoribbons, and at least some of the gates are provided at intersections of the first and second nanoribbons. Unlike previous approaches to quantum dot formation and manipulation, nanoribbon-based quantum dot devices provide strong spatial localization of the quantum dots, good scalability in the number of quantum dots included in the device, and/or design flexibility in making electrical connections to the quantum dot devices to integrate the quantum dot devices in larger computing devices.

A semiconductor device includes a substrate, a sensing device, and a transistor. The sensing device includes a dielectric layer, a sensing pad, a first sensing electrode, and a second sensing electrode. The dielectric layer is over the substrate. The sensing pad is over and in contact with the dielectric layer. The first sensing electrode and the second sensing electrode are over and in contact with the dielectric layer. The first sensing electrode and the second sensing electrode surround the sensing pad, and a distance between the first sensing electrode and the second sensing electrode is greater than a distance between the sensing pad and the first sensing electrode. The transistor is over the substrate. A gate of the transistor is connected to the sensing pad.

A silicon-based quantum device for confining charge carriers is provided. The device comprises: a substrate having a first planar region 137; a silicon layer 32 which forms part of the substrate and includes a step 33 with an edge 34 and a second planar region 135, wherein the second planar region 135 is substantially parallel to and offset from the first planar region 137; a first electrically insulating layer 42 provided on the silicon layer 32, overlying the step 33; a first metallic layer 51, provided on the first electrically insulating layer 42, overlying the step 33, arranged to be electrically connected such that a first confinement region 10 can be induced in which a charge carrier or charge carriers can be confined at the edge 34; and a second metallic layer 52, provided overlying the second planar region 135 of the silicon layer, wherein the second metallic layer is: electrically separated from the first metallic layer 51; and arranged to be electrically connected such that a second confinement region 11 can be induced in which a charge carrier or charge carriers can be confined only in the second planar region 135 of the silicon layer 32 under the second metallic layer 52, and the first confinement region 10 is couplable to the second confinement region 11; wherein the first confinement region 10 is displaced from the second confinement region 11 in a direction that is perpendicular to the edge 34. A method of assembling a silicon-based quantum device and a method of using a silicon-based quantum device are also provided.