Semiconductor devices configured to achieve a high withstand voltage are disclosed. In one example, a semiconductor device includes an SJ layer extending in a first direction and configured by alternately arraying semiconductor regions of a first conductivity type and semiconductor regions of a second conductivity type in a second direction orthogonal to the first direction. A first drain layer of the first conductivity type is electrically connected to the SJ layer on a first end side in the first direction, a channel layer of the second conductivity type is provided on the SJ layer on a second end side in the first direction, a first source layer of the first conductivity type is provided on the channel layer, and a first gate electrode is provided on a side of the channel layer and the first source layer in the first direction with a first insulating layer interposed therebetween.

A method for making a semiconductor device may include forming a first superlattice layer on a semiconductor substrate. The first superlattice layer may include a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The method may further include forming a first device layer on the first superlattice layer and comprising silicon, forming a second device layer on the first superlattice layer laterally adjacent the first device layer, with the second device layer comprising a Group III-N semiconductor, forming a first device on the first device layer, and forming a second device on the second device layer.

A semiconductor device may include a semiconductor substrate and a superlattice layer on the semiconductor substrate. The superlattice layer may include a plurality of stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The semiconductor device may also include a piezoelectric layer on the superlattice layer and comprising a Group III-N semiconductor.

A method for making a semiconductor device may include forming a superlattice layer on a first substrate and including a plurality of stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base silicon portions. The method may further include forming a Group III-N semiconductor stack comprising a plurality of layers of Group III-N semiconductor layers above the superlattice layer, and separating the Group III-N semiconductor stack from the first substrate at the superlattice layer.

A method for making a semiconductor device may include forming a semiconductor substrate, and forming a superlattice layer on the semiconductor substrate and including a plurality of stacked groups of layers. Each group of layers may including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The method may also include forming a Group III-N semiconductor stack comprising a plurality of layers of Group III-N semiconductor layers above the superlattice layer.

A semiconductor device may include a semiconductor substrate and a first superlattice layer on the semiconductor substrate. The first superlattice layer may include a plurality of stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The semiconductor device may further include a first device layer on the first superlattice layer and comprising silicon, a second device layer on the first superlattice layer laterally adjacent the first device layer, with the second device layer comprising a Group III-N semiconductor, a first device on the first device layer, and a second device on the second device layer.

An SiC semiconductor device includes a first SiC layer, a second SiC layer laminated on the first SiC layer, a first impurity region of a p-type formed in the first SiC layer, a second impurity region of the p-type formed in the second SiC layer, first inversion columns of an n-type that are formed at an interval in the first SiC layer such as to invert a conductivity type of the first impurity region; and second inversion columns of the n-type that are formed at an interval in the second SiC layer such as to invert a conductivity type of the second impurity region.