The present disclosure relates to semiconductor structures and, more particularly, to heterojunction bipolar transistors (HBTs) with a buried trap rich region and methods of manufacture. The structure includes: a trap rich isolation region embedded within the bulk substrate; and a heterojunction bipolar transistor above the trap rich isolation region, with its sub-collector region separated by the trap rich isolation region by a layer of the bulk substrate.

The present disclosure relates to semiconductor structures and, more particularly, to heterojunction bipolar transistors (HBTs) with a buried trap rich region and methods of manufacture. The structure includes: a trap rich isolation region embedded within the bulk substrate; and a heterojunction bipolar transistor above the trap rich isolation region, with its sub-collector region separated by the trap rich isolation region by a layer of the bulk substrate.

A light-emitting diode 100 includes a first region 1, for example of the P type, formed in a first layer 10 and forming, in a direction normal to a basal plane, a stack with a second region 2 having at least one quantum well formed in a second layer 20, and including a third region 3, for example of the N type, extending in the direction normal to the plane, bordering and in contact with the first and second regions 1, 2, through the first and second layers 10, 20. A process for producing a light-emitting diode 100 in which the third region 3 is formed by implantation into and through the first and second layers 10, 20.

An alternating electric field-driven gallium nitride (GaN)-based nano-light-emitting diode (nanoLED) structure with an electric field enhancement effect is provided. The GaN-based nanoLED structure forms a nanopillar structure that runs through an indium tin oxide (ITO) layer, a p-type GaN layer, a multiple quantum well (MQW) active layer and an n-type GaN layer and reaches a GaN buffer layer; and the nanopillar structure has a cross-sectional area that is smallest at the MQW active layer and gradually increases towards two ends of a nanopillar, forming a pillar structure with a thin middle and two thick ends. The shape of the GaN-based nanopillar improves the electric field strength within the QW layer in the alternating electric field environment and increases the current density in the QW region of the nanopillar structure under current driving, forming strong electric field gain and current gain, thereby improving the luminous efficiency of the device.

The presented devices and methods are directed to efficient and effective photon emission. In one embodiment, high-performance tunnel junction deep ultraviolet (UV) light-emitting diodes (LEDs) are created using plasma-assisted molecular beam epitaxy. The device heterostructure was grown under slightly Ga-rich conditions to promote the formation of nanoscale clusters in the active region. The nanoscale clusters can act as charge containment configurations. In one exemplary implementation, a device operates at approximately 255 nm light emission with a maximum external quantum efficiency (EPE) of 7.2% and wall-plug efficiency (WPE) of 4%, which are nearly one to two orders of magnitude higher than previously reported tunnel junction devices operating at this wavelength. The devices exhibit highly stable emission originating from highly localized carriers in Ga-rich regions formed in the active region, with nearly constant emission peak with increasing current density up to 200 A/cm.sup.2, due to the strong charge carrier confinement related to the presence of nanoclusters (e.g., Ga-rich) and radiative emission originating from highly localized carriers in Ga-rich regions formed in the active region

A semiconductor device and a method for manufacturing the same. The method comprise: forming a first field-effect transistor (FET) disposed on a substrate and a first isolation layer disposed on the first FET; forming a first through hole in the first isolation layer, where a metal layer is deposited in the first through hole and is electrically connected to the first FET; forming a second isolation layer, which is disposed on the first isolation layer and the metal layer; and forming a second FET which is disposed on the second isolation layer, where a second through hole is disposed in the second FET and the second isolation layer, a metal material filled in the second through hole serves as a first contact plug, and the first contact plug is electrically connected to the metal layer. The metal layer serves as a power distribution network for both FETs.

A nitride semiconductor device including a substrate, a channel layer, a carbon-poor barrier layer having a recess, a carbon-rich barrier layer disposed over the recess and the carbon-poor barrier layer, and a gate electrode above the recess, wherein the carbon-poor and carbon-rich barrier layers have bandgaps larger than that of the channel layer, the upper surface of the carbon-rich barrier layer includes a first main surface including a source electrode and a drain electrode, and a bottom surface of a depression disposed along the recess, and side surfaces of the depression connecting the first main surface to the bottom surface of the depression, and among edges of the depression of the carbon-rich barrier layer which are boundaries between the first main surface and the side surfaces of the depression, the edge of the depression of the carbon-rich barrier layer closest to the drain electrode is covered with the gate electrode.

A semiconductor device includes a plurality of gates formed upon a semiconductor substrate that includes a plurality of outer active areas (e.g. CMOS/PMOS areas, source/drain regions, etc.) and one or more inner active areas. An isolator is formed upon one or more inner gates associated with the one or more inner active areas. A contact bar electrically connects the outer active areas and/or outer gates and is formed upon the isolator. The isolator electrically insulates the contact bar from the one or more inner active areas and/or the one or more inner gates.

Methodologies and a device for SRAM patterning are provided. Embodiments include forming a spacer layer over a fin channel, the fin channel being formed in four different device regions; forming a bottom mandrel over the spacer layer; forming a top mandrel directly over the bottom mandrel, wherein the top and bottom mandrels including different materials; forming a buffer oxide layer over the top mandrel; forming an anti-reflective coating (ARC) over the first OPL; forming a photoresist (PR) over the ARC and patterning the PR; and etching the first OPL, ARC, buffer oxide, and top mandrel with the pattern of the PR, wherein a pitch of the PR as patterned is different in each of the four device regions.

An integrated circuit and method having an extended drain MOS transistor with a buried drift region, a drain diffused link, a channel diffused link, and an isolation link which electrically isolated the source, where the isolation diffused link is formed by implanting through segmented areas to dilute the doping to less than two-thirds the doping in the drain diffused link.