An embodiment includes a method including forming an opening in a cut metal gate region of a metal gate structure of a semiconductor device, conformally depositing a first dielectric layer in the opening, conformally depositing a silicon layer over the first dielectric layer, performing an oxidation process on the silicon layer to form a first silicon oxide layer, filling the opening with a second silicon oxide layer, performing a chemical mechanical polishing on the second silicon oxide layer and the first dielectric layer to form a cut metal gate plug, the chemical mechanical polishing exposing the metal gate structure of the semiconductor device, and forming a first contact to a first portion of the metal gate structure and a second contact to a second portion of the metal gate structure, the first portion and the second portion of the metal gate structure being separated by the cut metal gate plug.

An embodiment is a structure including a first fin over a substrate, a second fin over the substrate, the second fin being adjacent the first fin, an isolation region surrounding the first fin and the second fin, a gate structure along sidewalls and over upper surfaces of the first fin and the second fin, the gate structure defining channel regions in the first fin and the second fin, a source/drain region on the first fin and the second fin adjacent the gate structure, and an air gap separating the source/drain region from a top surface of the substrate.

A semiconductor device includes first and second nitride semiconductor layers. The second layer on the first nitride has a first region, a second region, and a third region between the first and second regions. A first gate electrode is in the first region and extends parallel to a surface of a substrate. A first source electrode is in the first region and extends in the first direction. A second gate electrode in the second region and extends in the first direction. A second source electrode is in the second region and extends in the first direction. A drain electrode coupled to a first and a second wiring. The first wiring directly contacts the second nitride semiconductor layer in the first region. The second wiring directly contacts the second nitride semiconductor layer in the second region. An insulation material is in the third region.

A semiconductor device including a FET includes an isolation insulating layer disposed in a trench of the substrate, a gate dielectric layer disposed over a channel region of the substrate, a gate electrode disposed over the gate dielectric layer, a source and a drain disposed adjacent to the channel region, and an embedded insulating layer disposed below the source, the drain and the gate electrode and both ends of the embedded insulating layer are connected to the isolation insulating layer.

A method of manufacturing a semiconductor device includes forming a fin structure in which first semiconductor layers and second semiconductor layers are alternatively stacked, the first and second semiconductor layers having different material compositions; forming a sacrificial gate structure over the fin structure; forming a gate spacer on sidewalls of the sacrificial gate structure; etching a source/drain (S/D) region of the fin structure, which is not covered by the sacrificial gate structure and the gate spacer, thereby forming an S/D trench; laterally etching the first semiconductor layers through the S/D trench, thereby forming recesses; selectively depositing an insulating layer on surfaces of the first and second semiconductor layers exposed in the recesses and the S/D trench, but not on sidewalls of the gate spacer; and growing an S/D epitaxial feature in the S/D trench, thereby trapping air gaps in the recesses.

A multi-finger transistor structure is provided in the present invention, including multiple active areas, a gate structure consisting of multiple gate parts and connecting parts, wherein each gate part crosses over one of the active areas and each connecting part alternatively connects one end and the other end of the gate parts so as to form a meander gate structure, and multiple sources and drains, wherein one source and one drain are set between two adjacent gate parts, and each gate parts is accompanied by one source and one drain at two sides respectively, and the distance between the drain and the gate part is larger than the distance between the source and the gate part, so that the source and the drain are asymmetric with respect to the corresponding gate part, and air gaps are formed in the dielectric layer between each drain and the corresponding gate part.

Embodiments of the invention are directed to a transistor device that includes a channel stack having stacked, spaced-apart, channel layers. A first source or drain (S/D) region is communicatively coupled to the channel stack. A tunnel extends through the channel stack, wherein the tunnel includes a central region and a first set of end regions. The first set of end regions is positioned closer to the first S/D region than the central region is to the first S/D region. A first type of work-function metal (WFM) is formed in the first set of end regions, the first WFM having a first work-function (WF). A second type of WFM is formed in the central region, the second type of WFM having a second WF, wherein the first WF is different than the second WF.

A first gate-all-around (GAA) transistor and a second GAA transistor may be formed on a substrate. The first GAA transistor includes at least one silicon plate, a first gate structure, a first source region, and a first drain region. The second GAA transistor includes at least one silicon-germanium plate, a second gate structure, a second source region, and a second drain region. The first GAA transistor may be an n-type field effect transistor, and the second GAA transistor may be a p-type field effect transistor. The gate electrodes of the first gate structure and the second gate structure may include a same conductive material. Each silicon plate and each silicon-germanium plate may be single crystalline and may have a same crystallographic orientation for each Miller index.

Material systems for source region, drain region, and a semiconductor body of transistor devices in which the semiconductor body is electrically insulated from an underlying substrate are selected to reduce or eliminate a band to band tunneling (BTBT) effect between different energetic bands of the semiconductor body and one or both of the source region and the drain region. This can be accomplished by selecting a material for the semiconductor body with a band gap that is larger than a band gap for material(s) selected for the source region and/or drain region.

The present disclosure relates to semiconductor structures and, more particularly, to metal-oxide semiconductor transistors and methods of manufacture. The structure includes: a substrate comprising a drift region and a body region; a gate structure between the drift region and the body region; an insulator material over the gate structure, the drift region and the body region; and an air gap within the insulator material and extending into the drift region.