A 3D semiconductor device including: a first level including a first single crystal layer and first transistors, which each include a single crystal channel; a first metal layer with an overlaying second metal layer; a second level including second transistors, overlaying the first level; a third level including third transistors, overlaying the second level; a fourth level including fourth transistors, overlaying the third level, where the second level includes first memory cells, where each of the first memory cells includes at least one of the second transistors, where the fourth level includes second memory cells, where each of the second memory cells includes at least one of the fourth transistors, where the first level includes memory control circuits, where second memory cells include at least four memory arrays, each of the four memory arrays are independently controlled, and at least one of the second transistors includes a metal gate.

A volatile memory array using vertical thyristors is disclosed together with methods of fabricating the array.

A volatile memory array using vertical thyristors is disclosed together with methods of fabricating the array.

An insulated gate turn-off thyristor has a layered structure including a p+ layer (e.g., a substrate), an n-epi layer, a p-well, vertical insulated gate regions formed in the p-well, and an n-layer over the p-well and between the gate regions, so that vertical npn and pnp transistors are formed. The p-well has an intermediate highly doped portion. When the gate regions are sufficiently biased, an inversion layer surrounds the gate regions, causing the effective base of the npn transistor to be narrowed to increase its beta. When the product of the betas exceeds one, controlled latch-up of the thyristor is initiated. The p-well's highly doped intermediate region enables improvement in the npn transistor efficiency as well as enabling more independent control over the characteristics of the n-type layer (emitter), the emitter-base junction characteristics, and the overall dopant concentration and thickness of the p-type base.

One embodiment of the present invention relates to a silicon-controlled-rectifier (SCR). The SCR includes a longitudinal silicon fin extending between an anode and a cathode and including a junction region there between. One or more first transverse fins traverses the longitudinal fin at one or more respective tapping points positioned between the anode and the junction region. Other devices and methods are also disclosed.

A volatile memory array using vertical thyristors is disclosed together with methods of fabricating the array.

A reverse conducting power semiconductor device includes a plurality of thyristor cells and a freewheeling diode are integrated in a semiconductor wafer. The freewheeling diode includes a diode anode layer, a diode anode electrode, a diode cathode layer, and a diode cathode electrode. The diode cathode layer includes diode cathode layer segments, each of which is stripe-shaped and arranged within a corresponding stripe-shaped first diode anode layer segment such that a longitudinal main axis of each diode cathode layer segment extends along the longitudinal main axis of the corresponding one of the first diode anode layer segments.

An insulated gate turn-off (IGTO) device, formed as a die, has a layered structure including a p+ layer (e.g., a substrate), an n epi layer, a p-well, an n-layer over the p-well, p+ regions over the n-layer, trenched gate regions formed in the p-well, and n+ regions between the gate regions, so that vertical npn and pnp transistors are formed. The device is formed of a matrix of cells. To turn the device on, a positive voltage is applied to the gate, referenced to the cathode. The cells contain a vertical p-channel MOSFET, for shorting the base of the npn transistor to its emitter, to turn the npn transistor off when the p-channel MOSFET is turned on by a slight negative voltage applied to the gate. One or more p-layers are implanted into the p-well, below the n-layer, for independently controlling the turn-on and turn-off threshold voltages and the breakdown voltage.