An integrated circuit (IC) device includes a stripe of material perpendicular to, and spanning between, semiconductor structures with multiple widths, and the stripe is between transistors with channel regions of differing widths in the semiconductor structures. The material stripes cover transition portions between different widths of the semiconductor structures. The semiconductor structures may be channel structures of different types, including groups of fins or nanoribbons. Channel regions of differing widths may include more or fewer fins or narrower or wider nanoribbons. The channel regions may have alternating conductivity types, n- and p-type.

A 3-dimensional array of NOR memory strings being organized by planes of NOR memory strings, in which (i) the storage transistors in the NOR memory strings situated in a first group of planes are configured to be programmed, erased, program-inhibited or read in parallel, and (ii) the storage transistors in NOR memory strings situated within a second group of planes are configured for storing resource management data relating to data stored in the storage transistors of the NOR memory strings situated within the first group of planes, wherein the storage transistors in NOR memory strings in the second group of planes are configured into sets.

Methods for improving profiles of channel regions in semiconductor devices and semiconductor devices formed by the same are disclosed. In an embodiment, a method includes forming a semiconductor fin over a semiconductor substrate, the semiconductor fin including germanium, a germanium concentration of a first portion of the semiconductor fin being greater than a germanium concentration of a second portion of the semiconductor fin, a first distance between the first portion and a major surface of the semiconductor substrate being less than a second distance between the second portion and the major surface of the semiconductor substrate; and trimming the semiconductor fin, the first portion of the semiconductor fin being trimmed at a greater rate than the second portion of the semiconductor fin.

Disclosed herein are dual gate trench shaped thin film transistors and related methods and devices. Exemplary thin film transistor structures include a non-planar semiconductor material layer having a first portion extending laterally over a first gate dielectric layer, which is over a first gate electrode structure, and a second portion extending along a trench over the first gate dielectric layer, a second gate electrode structure at least partially within the trench, and a second gate dielectric layer between the second gate electrode structure and the first portion.

A transistor structure includes a semiconductor body, a source region, a drain region and a gate region. The semiconductor body has a convex structure and the convex structure has at least four conductive channels extending upward. The source region contacts with a first end of the convex structure. The drain region contacts with a second end of the convex structure. The gate region has a gate conductive layer, wherein the gate conductive layer is across over the convex structure. Two or four conductive channels are not parallel to each other, and there is no shallow trench isolation region among the at least four conductive channels.

Gate-all-around integrated circuit structures having a removed substrate, and methods of fabricating gate-all-around integrated circuit structures having a removed substrate, are described. For example, an integrated circuit structure includes a vertical arrangement of horizontal nanowires. A gate stack surrounds a channel region of the vertical arrangement of horizontal nanowires. A pair of non-discrete epitaxial source or drain structures is at first and second ends of the vertical arrangement of horizontal nanowires. A pair of dielectric spacers is between the pair of non-discrete epitaxial source or drain structures and the gate stack. The pair of dielectric spacers and the gate stack have co-planar top surfaces. The pair of dielectric spacers, the gate stack and the pair of non-discrete epitaxial source or drain structures have co-planar bottom surfaces.

A semiconductor structure includes a fin disposed on a substrate, the fin including a channel region comprising a plurality of channels vertically stacked over one another, the channels comprising germanium distributed therein. The semiconductor structure further includes a gate stack engaging the channel region of the fin and gate spacers disposed between the gate stack and the source and drain regions of the fin, wherein each channel of the channels includes a middle section wrapped around by the gate stack and two end sections engaged by the gate spacers, wherein a concentration of germanium in the middle section of the channel is higher than a concentration of germanium in the two end sections of the channel, and wherein the middle section of the channel further includes a core portion and an outer portion surrounding the core portion with a germanium concentration profile from the core portion to the outer portion.

Provided herein may be a semiconductor memory device and a method of manufacturing the semiconductor memory device. The semiconductor memory device includes a stacked body including interlayer insulating layers and a select line disposed between the interlayer insulating layers, a core insulating layer penetrating the stacked body, a semiconductor pattern extending along a sidewall of the core insulating layer and including an undoped area disposed between the select line and the core insulating layer, doped semiconductor patterns disposed between the semiconductor pattern and the interlayer insulating layers, and a gate insulating layer disposed between the semiconductor pattern and the select line.

In certain aspects, a method of erasing a memory device is disclosed. The memory device includes a bottom select gate (BSG) and a dielectric trench separating the BSG into a first sub-BSG and a second sub-BSG. A first voltage is applied to the first sub-BSG. A second voltage is applied to the second sub-BSG. The second voltage is different from the first voltage.

An apparatus comprises a stack comprising an alternating sequence of dielectric structures and conductive structures, a first channel material extending vertically through the stack, and a second channel material adjacent the first channel material and extending vertically through the stack. The first channel material has a first band gap and the second channel material has a second band gap that is relatively larger than the first band gap. The apparatus further comprises a conductive plug structure adjacent to each of the first channel material and the second channel material, and a conductive line structure adjacent to the conductive plug structure. Methods of forming the apparatus, memory devices, and electronic systems are also described.