An epitaxial group-ill-nitride buffer-layer structure is provided on a heterosubstrate, wherein the buffer-layer structure has at least one stress-management layer sequence including an interlayer structure arranged between and adjacent to a first and a second group-ill-nitride layer, wherein the interlayer structure comprises a group-ill-nitride interlayer material having a larger band gap than the materials of the first and second group-ill-nitride layers, and wherein a p-type-dopant-concentration profile drops, starting from at least 11018 cm-3, by at least a factor of two in transition from the interlayer structure to the first and second group-ill-nitride layers.

A high-electron-mobility semiconductor device includes: a buffer region having first, second and third cross-sections forming a stepped lateral profile, the first cross-section being thicker than the third cross-section and comprising a first buried field plate disposed therein, the second cross-section interposed between the first and third cross-sections and forming oblique angles with the first and third cross-sections; and a barrier region of substantially uniform thickness extending along the stepped lateral profile of the buffer region, the barrier region being separated from the first buried field plate by a portion of the buffer region. The buffer region is formed by a first semiconductor material and the barrier region is formed by a second semiconductor material. The first and second semiconductor materials have different band-gaps such that an electrically conductive channel including a two-dimensional charge carrier gas arises at an interface between the buffer and barrier regions due to piezoelectric effects.

A semiconductor device includes a transistor, a semiconductor layer, an active region and a conductive layer. The active region is in the semiconductor layer. The conductive layer is configured to maintain a channel in the active region when the transistor is triggered to be conducted.

The semiconductor device includes a trench that penetrates a barrier layer, and reaches a middle portion of a channel layer among an n+ layer, an n-type layer, a p-type layer, the channel layer, and the barrier layer which are formed above a substrate, a gate electrode arranged within the groove through a gate insulating film, and a source electrode and a drain electrode which are formed above the barrier layer on both sides of the gate electrode. The n-type layer and the drain electrode are electrically coupled by a connection portion that reaches the n+ layer. The p-type layer and the source electrode are electrically coupled by a connection portion that reaches the p-type layer. A diode including a p-type layer and an n-type layer is provided between the source electrode and the drain electrode, to thereby prevent the breaking of an element caused by an avalanche breakdown.

A semiconductor device includes a substrate having an upper surface including a recess region, a semiconductor structure on the substrate, a portion of the semiconductor structure within the recess region, and a gate contact, a drain contact, and a source contact on the semiconductor structure. The recess region does not vertically overlap the drain contact or the source contact.

GaN based nanowires are used to grow high quality, discreet base elements with c-plane top surface for fabrication of various semiconductor devices, such as diodes and transistors for power electronics.

Methods for stress control in thin silicon (Si) wafer-based semiconductor materials. By a specific interrelation of process parameters (e.g., temperature, reactant supply, time), a highly uniform nucleation layer is formed on the Si substrate that mitigates and/or better controls the stress (tensile and compressive) in subsequent layers formed on the thin Si substrate.

The present disclosure involves a method of fabricating a semiconductor device. A surface of a silicon wafer is cleaned. A first buffer layer is then epitaxially grown on the silicon wafer. The first buffer layer contains an aluminum nitride (AlN) material. A second buffer layer is then epitaxially grown on the first buffer layer. The second buffer layer includes a plurality of aluminum gallium nitride (Al.sub.xGa.sub.1xN) sub-layers. Each of the sub-layers has a respective value for x that is between 0 and 1. A value of x for each sub-layer is a function of its position within the second buffer layer. A first gallium nitride (GaN) layer is epitaxially grown over the second buffer layer. A third buffer layer is then epitaxially grown over the first GaN layer. A second GaN layer is then epitaxially grown over the third buffer layer.

An epitaxial group-ill-nitride buffer-layer structure is provided on a heterosubstrate, wherein the buffer-layer structure has at least one stress-management layer sequence including an interlayer structure arranged between and adjacent to a first and a second group-ill-nitride layer, wherein the interlayer structure comprises a group-ill-nitride interlayer material having a larger band gap than the materials of the first and second group-ill-nitride layers, and wherein a p-type-dopant-concentration profile drops, starting from at least 11018 cm-3, by at least a factor of two in transition from the interlayer structure to the first and second group-ill-nitride layers.

A high electron mobility transistor (HEMT) device with a highly resistive layer co-doped with carbon (C) and a donor-type impurity and a method for making the HEMT device is disclosed. In one embodiment, the HEMT device includes a substrate, the highly resistive layer co-doped with C and the donor-type impurity formed above the substrate, a channel layer formed above the highly resistive layer, and a barrier layer formed above the channel layer. In one embodiment, the highly resistive layer comprises gallium nitride (GaN). In one embodiment, the donor-type impurity is silicon (Si). In another embodiment, the donor-type impurity is oxygen (O).