A 3D semiconductor device including: a first level including a first single crystal layer and first transistors, which each include a single crystal channel; a first metal layer with an overlaying second metal layer; a second level including second transistors, overlaying the first level; a third level including third transistors, overlaying the second level; a fourth level including fourth transistors, overlaying the third level, where the second level includes first memory cells, where each of the first memory cells includes at least one of the second transistors, where the fourth level includes second memory cells, where each of the second memory cells includes at least one of the fourth transistors, where the first level includes memory control circuits, where second memory cells include at least four memory arrays, each of the four memory arrays are independently controlled, and at least one of the second transistors includes a metal gate.

A cost effective process flow for manufacturing semiconductor on insulator structures is parallel is provided. Each of the multiple semiconductor-on-insulator composite structures prepared in parallel comprises a charge trapping layer (CTL).

A semiconductor device according to an embodiment includes a SiC layer having a first plane and a second plane, a gate insulating film provided on the first plane, a gate electrode provided on the gate insulating film, a first SiC region of a first conductivity type provided in the SiC layer, a second SiC region of a second conductivity type provided in the first SiC region, a third SiC region of the first conductivity type provided in the second SiC region, and a fourth SiC region of the first conductivity type provided between the second SiC region and the gate insulating film, the fourth SiC region interposed between the second SiC regions, and the fourth SiC region provided between the first SiC region and the third SiC region.

A method for depositing a layer on a semiconductor wafer by vapor deposition in a process chamber, involves removing native oxide from a surface of the wafer; and then depositing an epitaxial layer with a thickness of at least 40 m on the surface of the wafer by introducing a silicon containing gas and a carrier gas into the process chamber, wherein the flow rate of the silicon containing gas is lower than 10 standard liters per minute and the flow rate of the carrier gas is at least 40 standard liters per minute.

A method to improve the planarity of a semiconductor wafer and an assembly made from the method. In a preferred embodiment of the method, a compressive PECVD oxide layer such as SiO.sub.2 having a predetermined thickness or pattern is deposited on the second surface of a semiconductor wafer having an undesirable warp or bow. The thickness or pattern of the deposited oxide layer is determined by the measured warp or bow of the semiconductor wafer. The compressive oxide layer induces an offsetting compressive force on the second surface of the semiconductor wafer to reduce the warp and bow across the major surface of the semiconductor wafer.

The present invention provides a method of producing an epitaxial wafer having a highly flat rear surface without polishing top and rear surfaces of the epitaxial wafer after forming an epitaxial film. A method of producing an epitaxial wafer 100 according to the present invention comprises a step of preparing a semiconductor wafer 10 having a beveled portion 11 formed on its end portion, a first surface 12b, a second surface 12a opposite to the first surface 12b, and edges 13b and 13a on both of the first surface 12b and the second surface 12a, the each edge 13a and 13b is boundary with the beveled portion 11; a step of processing of rolling off an outer peripheral portion 14 of the first surface 12b to form a roll-off region, the outer peripheral portion 14 is extending outward of the wafer from a predetermined position P inner than the position of the edge 13b on 12a the first surface 12b; and a step of forming a first epitaxial film 20 on the second surface 12a.

A semiconductor device according to an embodiment includes a SiC layer having a first plane and a second plane, a gate insulating film provided on the first plane, a gate electrode provided on the gate insulating film, a first SiC region of a first conductivity type provided in the SiC layer, a second SiC region of a second conductivity type provided in the first SiC region, a third SiC region of the first conductivity type provided in the second SiC region, and a fourth SiC region of the first conductivity type provided between the second SiC region and the gate insulating film, the fourth SiC region interposed between the second SiC regions, and the fourth SiC region provided between the first SiC region and the third SiC region.

A method and an apparatus for manufacturing a silicon carbide single crystal, and a silicon carbide single crystal ingot, obtaining a silicon carbide single crystal reduced in defects such as threading dislocations, are provided. The method manufactures a silicon carbide single crystal by supplying a raw material gas into a reaction vessel with a seed substrate, and heats the interior to grow a silicon carbide single crystal on the surface of the seed substrate. The method includes growing the silicon carbide single crystal on the seed substrate surface, while controlling the temperature, to perform pair annihilation of threading dislocations or synthesis of the threading dislocations; and a second step of maintaining the temperature inside the reaction vessel in the state of the first predetermined temperature after execution of the first step, to bring the leading ends of the threading dislocations close to the surface of the seed substrate.

A method and an apparatus for manufacturing a silicon carbide single crystal, and a silicon carbide single crystal ingot, obtaining a silicon carbide single crystal reduced in defects such as threading dislocations, are provided. The method manufactures a silicon carbide single crystal by supplying a raw material gas into a reaction vessel with a seed substrate, and heats the interior to grow a silicon carbide single crystal on the surface of the seed substrate. The method includes growing the silicon carbide single crystal on the seed substrate surface, while controlling the temperature, to perform pair annihilation of threading dislocations or synthesis of the threading dislocations; and a second step of maintaining the temperature inside the reaction vessel in the state of the first predetermined temperature after execution of the first step, to bring the leading ends of the threading dislocations close to the surface of the seed substrate.

A gallium-containing nitride crystals are disclosed, comprising: a top surface having a crystallographic orientation within about 5 degrees of a plane selected from a (0001) +c-plane and a (000-1) c-plane; a substantially wurtzite structure; n-type electronic properties; an impurity concentration of hydrogen greater than about 510.sup.17 cm.sup.3; an impurity concentration of oxygen between about 210.sup.17 cm.sup.3 and about 110.sup.20 cm.sup.3; an [H]/[O] ratio of at least 0.3; an impurity concentration of at least one of Li, Na, K, Rb, Cs, Ca, F, and Cl greater than about 110.sup.16 cm.sup.3; a compensation ratio between about 1.0 and about 4.0; an absorbance per unit thickness of at least 0.01 cm.sup.1 at wavenumbers of approximately 3175 cm.sup.1, 3164 cm.sup.1, and 3150 cm.sup.1; and wherein, at wavenumbers between about 3200 cm.sup.1 and about 3400 cm.sup.1 and between about 3075 cm.sup.1 and about 3125 cm.sup.1, said gallium-containing nitride crystal is essentially free of infrared absorption peaks having an absorbance per unit thickness greater than 10% of the absorbance per unit thickness at 3175 cm.