Disclosed are a substrate regeneration method and a regenerated substrate. The substrate regeneration method comprises preparing a substrate having a surface separated from an epitaxial layer. The separated surface includes a convex portion and a concave portion, and the convex portion is comparatively flatter than the concave portion. A crystalline restoration layer is grown on the separated surface. The crystalline restoration layer is grown on the convex portion. Furthermore, a surface roughness improvement layer is grown on the crystalline restoration layer, thereby providing a continuous surface. Accordingly, it is possible to provide a regenerated substrate, which has a flat surface, without using physical polishing or chemical etching technology.

Methods for forming semiconductor structures are provided. The method for forming the semiconductor structure includes forming a word line cell over a substrate and forming a dielectric layer over the word line cell. The method further includes forming a conductive layer over the dielectric layer and polishing the conductive layer until the dielectric layer is exposed. The method further includes forming an oxide layer on a top surface of the conductive layer and removing portions of the conductive layer not covered by the oxide layer to form a memory gate.

In described examples, an embedded thermoelectric device is formed by forming isolation trenches in a substrate, concurrently between CMOS transistors and between thermoelectric elements of the embedded thermoelectric device. Dielectric material is formed in the isolation trenches to provide field oxide which laterally isolates the CMOS transistors and the thermoelectric elements. Germanium is implanted into the substrate in areas for the thermoelectric elements, and the substrate is subsequently annealed, to provide a germanium density of at least 0.10 atomic percent in the thermoelectric elements between the isolation trenches. The germanium may be implanted before the isolation trenches are formed, after the isolation trenches are formed and before the dielectric material is formed in the isolation trenches, and/or after the dielectric material is formed in the isolation trenches.

A three-dimensional (3D) semiconductor memory device that includes a peripheral logic structure including peripheral logic circuits disposed on a semiconductor substrate and a first insulation layer overlapping the peripheral logic circuits, and a plurality of memory blocks spaced apart from each other on the peripheral logic structure. At least one of the memory blocks includes a well plate electrode, a semiconductor layer in contact with a first surface of the well plate electrode, a stack structure including a plurality of electrodes vertically stacked on the semiconductor layer, and a plurality of vertical structures penetrating the stack structure and connected to the semiconductor layer.

The present invention provides a semiconductor device, including a substrate, two gate structures disposed on a channel region of the substrate, an epitaxial layer disposed in the substrate between two gate structures, a first dislocation disposed in the epitaxial layer, wherein the profile of the first dislocation has at least two non-parallel slanting lines, and a second dislocation disposed adjacent to a top surface of the epitaxial layer, and the profile of the second dislocation has at least two non-parallel slanting lines.

A semiconductor device according to an embodiment includes a SiC layer having a first plane and a second plane, a gate insulating film provided on the first plane, a gate electrode provided on the gate insulating film, a first SiC region of a first conductivity type provided in the SiC layer, a second SiC region of a second conductivity type provided in the first SiC region, a third SiC region of the first conductivity type provided in the second SiC region, and a fourth SiC region of the first conductivity type provided between the second SiC region and the gate insulating film, the fourth SiC region interposed between the second SiC regions, and the fourth SiC region provided between the first SiC region and the third SiC region.

A method of manufacturing a semiconductor device includes: forming a lattice defect layer in a substrate having a front surface region where a bipolar element of a pn junction type is formed and a rear surface region opposing the front surface region, the lattice defect layer being formed by injecting a charged particle to a first region in the rear surface region of the substrate; forming a laminated region, in which a first conductivity type impurity region and a second conductivity type impurity region are sequentially laminated from a rear surface side of the substrate toward the first region, in a second region in the rear surface region of the substrate, the first region being positioned deeper than the second region from a rear surface of the substrate; and selectively activating the laminated region by laser annealing after the formation of the laminated region and the lattice defect layer.

A semiconductor device includes: an electron transit layer constituted of GaN; an electron supply layer constituted of In.sub.x1Al.sub.y1Ga.sub.1x1y1N (0x1<1, 0y1<1, 0<1x1y1<1) and provided on the electron transit layer; a source electrode and a drain electrode that are provided on the electron supply layer and located apart from each other; a threshold voltage adjustment layer constituted of In.sub.x2Al.sub.y2Ga.sub.1x2y2N (0x2<1, 0y2<1, 0<1x2y21) of a p-type and provided on a part of the electron supply layer located between the source electrode and the drain electrode; and a gate electrode provided on the threshold voltage adjustment layer. A high resistance layer is respectively interposed both between the gate electrode and the threshold voltage adjustment layer, and between the threshold voltage adjustment layer and the electron supply layer.

A semiconductor device includes a substrate; a hydrogen insulating layer disposed on the substrate and including hydrogen ions; a first level layer disposed on the substrate and including a first wire and a second wire; a second level layer disposed on the substrate at a different level from the first level layer and including a third wire; an interlayer insulating layer disposed between the first level layer and the second level layer; a diffusion prevention layer contacting the third wire; a contact plug penetrating the interlayer insulating layer and electrically connecting the second wire to the third wire; and a dummy contact plug penetrating the interlayer insulating layer. The dummy contact plug contacts the first and second level layers, is spaced apart from the diffusion prevention layer, and is configured to provide a movement path for the hydrogen ions in the hydrogen insulating layer.

The present invention provides a nitride semiconductor substrate having an initial nitride and a nitride semiconductor sequentially stacked on one principal plane of a base substrate, wherein the nitride semiconductor substrate comprises recesses depressed from an interface between the base substrate and the initial nitride toward the base substrate along one arbitrary cross section; the recesses each have a diameter of 6 nm or more and 60 nm or less and are formed at a density of 310.sup.8 pieces/cm.sup.2 or more and 110.sup.11 pieces/cm.sup.2 or less; and the recess preferably has a depth of 3 nm or more and 45 nm or less from the interface between the base substrate and the initial nitride toward the base substrate.