A semiconductor device includes a substrate, a gate electrode in the substrate, a channel region above the gate electrode, a gate dielectric layer between the gate electrode and the channel region, and at least two source/drain regions in contact with the channel region. The channel region includes at least one boron-carbon-nitrogen single-walled nanotube (BCN-SWNT).

A photoluminescent liquid crystal display includes: a liquid crystal panel including a lower substrate, an upper substrate, a liquid crystal layer interposed between the upper and lower substrates, and a photoluminescent color filter layer disposed between the upper substrate and the liquid crystal layer; an optical device disposed on the upper substrate; a polarizing plate disposed under the lower substrate; and a backlight unit disposed under the polarizing plate and which emits blue light, where the photoluminescent color filter layer includes a first color filter which emits polarized red light, a second color filter which emits polarized green light, and a third color filter which emits polarized blue light, and the first color filter and the second color filter include a semiconductor nanocrystal-polymer composite.

Device architectures based on trapping and de-trapping holes or electrons and/or recombination of both types of carriers are obtained by carrier trapping either in near-interface deep ambipolar states or in quantum wells/dots, either serving as ambipolar traps in semiconductor layers or in gate dielectric/barrier layers. In either case, the potential barrier for trapping is small and retention is provided by carrier confinement in the deep trap states and/or quantum wells/dots. The device architectures are usable as three terminal or two terminal devices.

A photoluminescent liquid crystal display includes: a liquid crystal panel including a lower substrate, an upper substrate, a liquid crystal layer interposed between the upper and lower substrates, and a photoluminescent color filter layer disposed between the upper substrate and the liquid crystal layer; an optical device disposed on the upper substrate; a polarizing plate disposed under the lower substrate; and a backlight unit disposed under the polarizing plate and which emits blue light, where the photoluminescent color filter layer includes a first color filter which emits polarized red light, a second color filter which emits polarized green light, and a third color filter which emits polarized blue light, and the first color filter and the second color filter include a semiconductor nanocrystal-polymer composite.

Device architectures based on trapping and de-trapping holes or electrons and/or recombination of both types of carriers are obtained by carrier trapping either in near-interface deep ambipolar states or in quantum wells/dots, either serving as ambipolar traps in semiconductor layers or in gate dielectric/barrier layers. In either case, the potential barrier for trapping is small and retention is provided by carrier confinement in the deep trap states and/or quantum wells/dots. The device architectures are usable as three terminal or two terminal devices.

A threshold voltage tuning approach for forming a stacked nanowire gate-all around pFET is provided. In the present application, selective condensation (i.e., oxidation) is used to provide a threshold voltage shift in silicon germanium alloy nanowires. The threshold voltage shift is well controlled because both underlying parameters which govern the final germanium content, i.e., nanowire width and amount of condensation, are well controlled by the selective condensation process. The present application can address the problem of width quantization in stacked nanowire FETs by offering various device options.

A threshold voltage tuning approach for forming a stacked nanowire gate-all around pFET is provided. In the present application, selective condensation (i.e., oxidation) is used to provide a threshold voltage shift in silicon germanium alloy nanowires. The threshold voltage shift is well controlled because both underlying parameters which govern the final germanium content, i.e., nanowire width and amount of condensation, are well controlled by the selective condensation process. The present application can address the problem of width quantization in stacked nanowire FETs by offering various device options.

Aspects disclosed in the detailed description include nanowire channel structures of continuously stacked heterogeneous nanowires for complementary metal oxide semiconductor (CMOS) devices. Each of the nanowires has a top end portion and a bottom end portion that are narrower than a central portion. Furthermore, vertically adjacent nanowires are interconnected at the narrower top end portions and bottom end portions. This allows for connectivity between stacked nanowires and for having separation areas between vertically adjacent heterogeneous nanowires. Having the separation areas allows for gate material to be disposed over a large area of the heterogeneous nanowires and, therefore, provides strong gate control, a shorter nanowire channel structure, low parallel plate parasitic capacitance, and low parasitic channel capacitance. Having the nanowires be heterogeneous, i.e., fabricated using materials of different etching sensitivity, facilitates forming the particular cross section of the nanowires, thus eliminating the use of sacrificial masks/layers to form the heterogeneous nanowires.

A quantum rod includes a core of ZnS semiconductor particle having a rod shape; and a transition metal with which the core is doped and which is biased at one side of a length direction of the core.

Device architectures based on trapping and de-trapping holes or electrons and/or recombination of both types of carriers are obtained by carrier trapping either in near-interface deep ambipolar states or in quantum wells/dots, either serving as ambipolar traps in semiconductor layers or in gate dielectric/barrier layers. In either case, the potential barrier for trapping is small and retention is provided by carrier confinement in the deep trap states and/or quantum wells/dots. The device architectures are usable as three terminal or two terminal devices.