Embodiments of this disclosure relate to methods for removing a dummy material from under a superlattice structure. In some embodiments, after removing the dummy material, it is replaced with a bottom dielectric isolation layer beneath the superlattice structure.

A semiconductor device may include a substrate having a channel recess therein, a plurality of spaced apart shallow trench isolation (STI) regions in the substrate, and source and drain regions spaced apart in the substrate and between a pair of the STI regions. A superlattice channel may be in the channel recess of the substrate and extend between the source and drain regions, with the superlattice channel including a plurality of stacked group of layers, and each group of layers of the superlattice channel including stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. A replacement gate may be over the superlattice channel.

In an embodiment, a substrate structure includes a support substrate, a buffer structure arranged on the support substrate, the buffer structure including an intentionally doped superlattice laminate, an unintentionally doped first Group III nitride layer arranged on the buffer structure, a second Group III nitride layer arranged on the first Group III nitride layer forming a heterojunction therebetween, and a blocking layer arranged between the heterojunction and the buffer structure. The blocking layer is configured to block charges from entering the buffer structure.

A semiconductor device may include a substrate having a channel recess therein, a plurality of spaced apart shallow trench isolation (STI) regions in the substrate, and source and drain regions spaced apart in the substrate and between a pair of the STI regions. A superlattice channel may be in the channel recess of the substrate and extend between the source and drain regions, with the superlattice channel including a plurality of stacked group of layers, and each group of layers of the superlattice channel including stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. A replacement gate may be over the superlattice channel.

Embodiments of this disclosure relate to methods for removing a dummy material from under a superlattice structure. In some embodiments, after removing the dummy material, it is replaced with a bottom dielectric isolation layer beneath the superlattice structure.

A method for making a semiconductor device may include implanting non-semiconductor atoms into a localized region of a semiconductor layer, and forming a superlattice on the semiconductor layer over the localized region. The superlattice may include a stacked groups of layers, with each group of layers including stacked base semiconductor monolayers defining a base semiconductor portion, and at least one monolayer of the non-semiconductor atoms constrained within a crystal lattice of adjacent base semiconductor portions. The method may also include performing a thermal treatment to cause non-semiconductor atoms from the superlattice to be displaced, and to cause non-semiconductor atoms from the localized region to migrate into the superlattice and replace at least some of the displaced non-semiconductor atoms.

A nitride semiconductor element capable of accommodating GaN electron transfer layers of a wide range of thickness, so as to allow greater freedom of device design, and a nitride semiconductor element package with excellent voltage tolerance performance and reliability. On a substrate, a buffer layer including an AlN layer, a first AlGaN layer and a second AlGaN layer is formed. On the buffer layer, an element action layer including a GaN electron transfer layer and an AlGaN electron supply layer is formed. Thus, an HEMT element is constituted.