A method of forming a semiconductor device includes forming a contact metal layer, forming a channel structure on the contact metal layer, wherein the channel structure comprises a first source/drain region, a channel region and a second source/drain region stacked in that order, and forming a gate structure around the channel region, such that an upper surface of the gate structure is substantially coplanar with an upper surface of the channel structure.

A method of forming a semiconductor device includes forming a contact metal layer, forming a channel structure on the contact metal layer, wherein the channel structure comprises a first source/drain region, a channel region and a second source/drain region stacked in that order, and forming a gate structure around the channel region, such that an upper surface of the gate structure is substantially coplanar with an upper surface of the channel structure.

According to one embodiment of the present invention, an electronic device includes: a carbon layer including graphene, a thin film layer formed on the carbon layer, a channel layer formed on the thin film layer, a current cutoff layer formed between the thin film layer and the channel layer so as to cut off the flow of current between the thin film layer and the channel layer, and a source electrode and a drain electrode formed on the channel layer.

The embodiments of the present invention provides an oxide TFT, an array substrate and a display device, an oxide channel layer of the oxide TFT comprises a front channel oxide layer and a back channel oxide layer, a conduction band bottom of the back channel oxide layer being higher than a conduction band bottom of the front channel oxide layer, and a band gap of the back channel oxide layer being larger than a band gap of the front channel oxide layer. In the oxide TFT, the array substrate and the display device provided in the present invention, it is possible to accumulate a large number of electrons through the potential difference formed between oxide channel layers of a multilayer structure so as to increase the carrier concentration in the oxide channel layers to achieve the purpose of improving TFT mobility without damaging TFT stability.

A method of manufacturing ZnO-containing semiconductor structure includes steps of: (a) forming a subsidiary lamination, including alternately laminating at least two periods of active oxygen layers and ZnO-containing semiconductor layers doped with at least one species of group 3B element; (b) alternately laminating said subsidiary lamination and AgO layer, sandwiching an active oxygen layer, to form lamination structure; and (c) carrying out annealing in atmosphere in which active oxygen exists and pressure is below 10.sup.2 Pa, intermittently irradiating oxygen radical beam on a surface of said lamination structure, forming a p-type ZnO-containing semiconductor structure co-doped with said group 3B element and Ag.

According to one embodiment, a field-effect transistor includes a source region of a first conductivity type, a drain region of the first conductivity type and a channel region of the first conductivity type between the source region and the drain region, the source region, the drain region and the channel region being disposed in a polycrystalline semiconductor layer; a first layer including an amorphous semiconductor layer disposed on the channel region; a gate insulating layer disposed on the first layer; and a gate electrode disposed on the gate insulating layer.

A semiconductor nanocrystal including a core comprising a first semiconductor material comprising at least three chemical elements and a shell disposed over at least a portion of the core, the shell comprising a second semiconductor material, wherein the semiconductor nanocrystal is capable of emitting light with an improved photoluminescence quantum efficiency. Also disclosed are populations of semiconductor nanocrystals, compositions and devices including a semiconductor nanocrystal capable of emitting light with an improved photoluminescence quantum efficiency. In one embodiment, a semiconductor nanocrystal includes a core comprising a first semiconductor material comprising at least three chemical elements and a shell disposed over at least a portion of the core, the shell comprising a second semiconductor material, wherein the semiconductor nanocrystal is capable of emitting light upon excitation with a photoluminescence quantum efficiency greater than about 65%. In another embodiment, a semiconductor nanocrystal includes a core comprising a first semiconductor material comprising zinc, cadmium, and sulfur and a shell disposed over at least a portion of the core, the shell comprising a second semiconductor material. In a further embodiment, a semiconductor nanocrystal includes a core comprises a first semiconductor material comprising at least three chemical elements and a shell disposed over at least a portion of the core, the shell comprising a second semiconductor material comprising at least three chemical elements, wherein the semiconductor nanocrystal is capable of emitting light with a photoluminescence quantum efficiency greater than about 60% upon excitation. In a further embodiment, a semiconductor nanocrystal including a core comprises a first semiconductor material comprising zinc, cadmium, and selenium and a shell disposed over at least a portion of the core, the shell comprising a second semiconductor material, wherein the semiconductor nanocrystal is capable of emitting light with a photoluminescence quantum efficiency greater than about 60% upon excitation.

The invention provides semiconductor materials including a gallium nitride material layer formed on a silicon substrate and methods to form the semiconductor materials. The semiconductor materials include a transition layer formed between the silicon substrate and the gallium nitride material layer. The transition layer is compositionally-graded to lower stresses in the gallium nitride material layer which can result from differences in thermal expansion rates between the gallium nitride material and the substrate. The lowering of stresses in the gallium nitride material layer reduces the tendency of cracks to form. Thus, the invention enables the production of semiconductor materials including gallium nitride material layers having few or no cracks. The semiconductor materials may be used in a number of microelectronic and optical applications.

A quantum rod includes a core of ZnS semiconductor particle having a rod shape; and a transition metal with which the core is doped and which is biased at one side of a length direction of the core.

A method of forming a semiconductor device includes forming a contact metal layer, forming a channel structure on the contact metal layer, wherein the channel structure comprises a first source/drain region, a channel region and a second source/drain region stacked in that order, and forming a gate structure around the channel region, such that an upper surface of the gate structure is substantially coplanar with an upper surface of the channel structure.