Embodiments of the present disclosure provide a semiconductor device structure and methods of forming the same. The structure includes a source/drain region disposed over a substrate, an interlayer dielectric layer disposed over the source/drain region, a first conductive feature disposed over the source/drain region, a gate electrode layer disposed over the substrate, and a dielectric layer surrounding the first conductive feature. The dielectric layer includes a first portion disposed between the interlayer dielectric layer and the first conductive feature and a second portion disposed between the first conductive feature and the gate electrode layer, at least a portion of the first portion has a first thickness, and the second portion has a second thickness substantially greater than the first thickness.

A nitride semiconductor device includes a SiC substrate having a hexagonal crystal structure and including a main surface inclined with respect to a c-plane at an off-angle from 2 to 6 in a specific crystal direction, a nitride semiconductor layer located on the main surface of the SiC substrate and including an electron transit layer and an electron supply layer, and a gate electrode, a source electrode, and a drain electrode located on the nitride semiconductor layer. The main surface is parallel to a first direction, a second direction orthogonal to the first direction, and a third direction coinciding with the specific crystal direction in plan view. The source electrode and the drain electrode are separated in the first direction. The gate electrode extends in the second direction between the source electrode and the drain electrode. The first direction intersects the third direction at an angle of 9015.

The semiconductor device of the present invention includes a semiconductor substrate, a switching element which is defined on the semiconductor substrate, and a temperature sense element which is provided on the surface of the semiconductor substrate independently from the switching element and characterized by being dependent on a temperature.

The semiconductor device of the present invention includes a semiconductor substrate, a switching element which is defined on the semiconductor substrate, and a temperature sense element which is provided on the surface of the semiconductor substrate independently from the switching element and characterized by being dependent on a temperature.

Embodiments herein relate to systems, apparatuses, or processes directed to a package for wideband sub-terahertz communication, where the package includes a mixer and an amplifier, such as a power amplifier or a low noise amplifier, that are implemented within a layer of III-V material. Other embodiments may be described and/or claimed.

Disclosed are a thin film transistor, a method of manufacturing the same, and an array substrate. The thin film transistor includes a substrate, a gate, a gate insulating layer, an active layer, an ohmic contact layer, and a source-drain electrode layer, the gate insulating layer includes at least a first gate insulating layer deposited at a low rate, a second gate insulating layer deposited at a high rate, and a third gate insulating layer deposited at a low rate, the first gate insulating layer is in contact with the gate, the third gate insulating layer is in contact with the active layer, and the first gate insulating layer and the third gate insulating layer have a density greater than a density of the second gate insulating layer.

Ions are implanted into a first wafer through a top side, generating an ion damaged layer underneath the substrate film of the first wafer. A stress inducing layer is applied on a surface on the top side of the first wafer on one of the ion implanted side and the opposite side. The substrate film is separated from the first wafer at the ion damaged layer. the separated substrate film is bonded to a second wafer at a surface on one of a first side and a second side that this opposite of the first side of the second wafer to form an engineered wafer.

Structures and methods are disclosed in which a layer stack can be formed with a plurality of layers of a metal, where each of the layers of metal can be separated by a layer of a dielectric. An opening in the layer stack can be formed such that a semiconductor layer beneath the plurality of layers of the metal is uncovered. One or more vertical channel structures can be formed within the opening by epitaxial growth. The vertical channel structure can include a vertically oriented transistor. The vertical channel structure can include an interface of a silicide metal with a first metal layer of the plurality of metal layers. The interface can correspond to one of a source or a drain connection of a transistor. The silicide metal can be annealed above a temperature threshold to form a silicide interface between the vertical channel structure and the first metal layer.

A first gate-all-around (GAA) transistor and a second GAA transistor may be formed on a substrate. The first GAA transistor includes at least one silicon plate, a first gate structure, a first source region, and a first drain region. The second GAA transistor includes at least one silicon-germanium plate, a second gate structure, a second source region, and a second drain region. The first GAA transistor may be an n-type field effect transistor, and the second GAA transistor may be a p-type field effect transistor. The gate electrodes of the first gate structure and the second gate structure may include a same conductive material. Each silicon plate and each silicon-germanium plate may be single crystalline and may have a same crystallographic orientation for each Miller index.

Methods and structures for forming strained-channel finFETs are described. Fin structures for finFETs may be formed using two epitaxial layers of different lattice constants that are grown over a bulk substrate. A first thin, strained, epitaxial layer may be cut to form strain-relieved base structures for fins. The base structures may be constrained in a strained-relieved state. Fin structures may be epitaxially grown in a second layer over the base structures. The constrained base structures can cause higher amounts of strain to form in the epitaxially-grown fins than would occur for non-constrained base structures.