In an example, for manufacturing a semiconductor device, first dopants are implanted through a first surface section of a first surface of a silicon carbide body. A trench is formed that extends from the first surface into the silicon carbide body. The trench includes a first sidewall surface and an opposite second sidewall surface. A spacer mask is formed. The spacer mask covers at least the first sidewall surface. Second dopants are implanted through a portion of a bottom surface of the trench exposed by the spacer mask. The first dopants and the second dopants have a same conductivity type. The first dopants and the second dopants are activated. The first dopants form a doped top shielding region adjoining the second sidewall surface. The second dopants form a doped buried shielding region adjoining the bottom surface.

A nitride semiconductor device includes a SiC substrate having a hexagonal crystal structure and including a main surface inclined with respect to a c-plane at an off-angle from 2 to 6 in a specific crystal direction, a nitride semiconductor layer located on the main surface of the SiC substrate and including an electron transit layer and an electron supply layer, and a gate electrode, a source electrode, and a drain electrode located on the nitride semiconductor layer. The main surface is parallel to a first direction, a second direction orthogonal to the first direction, and a third direction coinciding with the specific crystal direction in plan view. The source electrode and the drain electrode are separated in the first direction. The gate electrode extends in the second direction between the source electrode and the drain electrode. The first direction intersects the third direction at an angle of 9015.

The semiconductor device of the present invention includes a semiconductor substrate, a switching element which is defined on the semiconductor substrate, and a temperature sense element which is provided on the surface of the semiconductor substrate independently from the switching element and characterized by being dependent on a temperature.

An embodiment is a structure including a first fin over a substrate, a second fin over the substrate, the second fin being adjacent the first fin, an isolation region surrounding the first fin and the second fin, a gate structure along sidewalls and over upper surfaces of the first fin and the second fin, the gate structure defining channel regions in the first fin and the second fin, a source/drain region on the first fin and the second fin adjacent the gate structure, and an air gap separating the source/drain region from a top surface of the substrate.

Methods for improving profiles of channel regions in semiconductor devices and semiconductor devices formed by the same are disclosed. In an embodiment, a method includes forming a semiconductor fin over a semiconductor substrate, the semiconductor fin including germanium, a germanium concentration of a first portion of the semiconductor fin being greater than a germanium concentration of a second portion of the semiconductor fin, a first distance between the first portion and a major surface of the semiconductor substrate being less than a second distance between the second portion and the major surface of the semiconductor substrate; and trimming the semiconductor fin, the first portion of the semiconductor fin being trimmed at a greater rate than the second portion of the semiconductor fin.

Material systems for source region, drain region, and a semiconductor body of transistor devices in which the semiconductor body is electrically insulated from an underlying substrate are selected to reduce or eliminate a band to band tunneling (BTBT) effect between different energetic bands of the semiconductor body and one or both of the source region and the drain region. This can be accomplished by selecting a material for the semiconductor body with a band gap that is larger than a band gap for material(s) selected for the source region and/or drain region.

A semiconductor device and a method for manufacturing the same. The semiconductor device comprises an n-channel GAA transistor and a p-channel GAA transistor, which are spaced apart. Each of the n-channel GAA transistor and the p-channel GAA transistor comprises a source, a drain, and at least one nanostructure layer located between the source and the drain. The p-channel GAA transistor further comprises a gate stack structure and a gate sidewall. In the p-channel GAA transistor, the at least one nanostructure layer comprises a channel portion that is covered by the gate stack structure and a connecting portion that is covered by the gate sidewall, and germanium content in the channel portion is greater than germanium content in the connecting portion and is greater than germanium content in the at least one nanostructure layer of the n-channel GAA transistor.

In a method of manufacturing a semiconductor device, a fin structure in which first semiconductor layers and second semiconductor layers are alternately stacked is formed, a sacrificial gate structure is formed over the fin structure, a source/drain region of the fin structure, which is not covered by the sacrificial gate structure, is etched, thereby forming a source/drain space, the first semiconductor layers are laterally etched through the source/drain space, and a source/drain epitaxial layer is formed in the source/drain space. An inner spacer made of a dielectric material is formed on an end of each of the etched first semiconductor layers and at least one of the spacer has width changes along vertical direction of device. At least one of the first semiconductor layers has a composition different from another of the first semiconductor layers.

The present disclosure describes a semiconductor device includes a substrate, a buffer layer on the substrate, and a stacked fin structure on the buffer layer. The buffer layer can include germanium, and the stacked fin structure can include a semiconductor layer with germanium and tin. The semiconductor device further includes a gate structure wrapped around a portion of the semiconductor layer and an epitaxial structure on the buffer layer and in contact with the semiconductor layer. The epitaxial structure includes germanium and tin.

A method for fabricating semiconductor devices is disclosed. The method includes forming a first fin structure and a second fin structure in a first region and a second region of a substrate, respectively, wherein the first and second fin structure and the substrate comprise a first semiconductor material; forming a first liner structure and a second liner structure at least extending along sidewalls of the first fin structure and sidewalls of the second fin structure, respectively; replacing an upper portion of the second fin structure with a second semiconductor material, while leaving the first fin structure substantially intact; and exposing a top surface and upper sidewalls of the first fin structure, and a top surface and upper sidewalls of the second fin structure.