In an example, for manufacturing a semiconductor device, first dopants are implanted through a first surface section of a first surface of a silicon carbide body. A trench is formed that extends from the first surface into the silicon carbide body. The trench includes a first sidewall surface and an opposite second sidewall surface. A spacer mask is formed. The spacer mask covers at least the first sidewall surface. Second dopants are implanted through a portion of a bottom surface of the trench exposed by the spacer mask. The first dopants and the second dopants have a same conductivity type. The first dopants and the second dopants are activated. The first dopants form a doped top shielding region adjoining the second sidewall surface. The second dopants form a doped buried shielding region adjoining the bottom surface.

An improved silicon carbide (SiC) super junction (SJ) MOSFET having at least two buried P-shield (BPS) regions facing each other for gate oxide electric-field and saturation current reductions is disclosed. The two BPS regions are spaced apart from a body region and formed either adjoining sidewalls or below a bottom of a P column region. Moreover, a saturation current pitching (SCP) structure formed in a Junction Field Effect Transistor (JFET) region sandwiched between the two BPS regions limits saturation current of the device in a forward conduction stage for the short-circuit capability improvement.

A nitride semiconductor device includes a SiC substrate having a hexagonal crystal structure and including a main surface inclined with respect to a c-plane at an off-angle from 2 to 6 in a specific crystal direction, a nitride semiconductor layer located on the main surface of the SiC substrate and including an electron transit layer and an electron supply layer, and a gate electrode, a source electrode, and a drain electrode located on the nitride semiconductor layer. The main surface is parallel to a first direction, a second direction orthogonal to the first direction, and a third direction coinciding with the specific crystal direction in plan view. The source electrode and the drain electrode are separated in the first direction. The gate electrode extends in the second direction between the source electrode and the drain electrode. The first direction intersects the third direction at an angle of 9015.

The semiconductor device of the present invention includes a semiconductor substrate, a switching element which is defined on the semiconductor substrate, and a temperature sense element which is provided on the surface of the semiconductor substrate independently from the switching element and characterized by being dependent on a temperature.

A power semiconductor device includes a substrate of a first conductivity type, a drift layer of a first conductivity type on the substrate, a well region of a second conductivity type on the drift layer, a source region of the first conductivity type on the well region, a gate electrode disposed in a gate trench penetrating through the source region and the well region, a first gate insulating layer, a second gate insulating layer, and a third gate insulating layer sequentially disposed between the well region and the gate electrode, a dielectric layer on the gate electrode, and a drain electrode on a lower surface of the substrate.

A method of manufacturing a silicon carbide semiconductor device includes preparing a silicon carbide semiconductor substrate in which, on a front surface of a starting substrate of a first conductivity type, a first semiconductor layer of the first conductivity type is provided, the first semiconductor layer having an impurity concentration lower than an impurity concentration of the starting substrate. Next, at the surface of the first semiconductor layer, a second semiconductor layer of a second conductivity type is formed. Next, at the surface of the second semiconductor layer, an ohmic electrode is formed. Next, at the surface of the ohmic electrode, a Ti film and a TiN film are sequentially deposited to form a barrier metal. Next, the barrier metal is subjected to a heat treatment to form an annealed barrier metal. The heat treatment is performed in a range of 550 degrees C. to 750 degrees C.

A method for forming an interface layer on a silicon carbide body comprises removing an oxide layer from a surface of a silicon carbide body to obtain a silicon carbide surface. The silicon carbide body comprises a source region of a first conductivity type and a body region of a second conductivity type. The method further comprises after removing the oxide layer, depositing an interface layer directly on the silicon carbide surface. The interface layer has a thickness of less or equal to 15 nm. The method further comprises forming an electrical insulator over the interface layer, and forming a gate electrode over the electrical insulator.

An SiC semiconductor device includes an SiC chip having a first main surface at one side and a second main surface at another side, a first main surface electrode including a first Al layer and formed on the first main surface, a pad electrode formed on the first main surface electrode and to be connected to a lead wire, and a second main surface electrode including a second Al layer and formed on the second main surface.

An embodiment is a structure including a first fin over a substrate, a second fin over the substrate, the second fin being adjacent the first fin, an isolation region surrounding the first fin and the second fin, a gate structure along sidewalls and over upper surfaces of the first fin and the second fin, the gate structure defining channel regions in the first fin and the second fin, a source/drain region on the first fin and the second fin adjacent the gate structure, and an air gap separating the source/drain region from a top surface of the substrate.

A metal oxide semiconductor field effect transistor (MOSFET) device and a manufacturing method therefor. A first implantation region easy to diffuse and a second implantation region which is not easy to diffuse and has a deeper junction are formed in sequence. After ion implantation in a source region and the like is completed, the first implantation region is activated to form a required well region in a mode of junction diffusion in the first implantation region, and the second implantation region is used for increasing the depth of the well region, thereby avoiding the damage to the surface of a substrate at a channel and roughness of the surface of the channel of the device caused by the formation of a P well directly through multiple Al ion implantation. Besides, the ion implantation in the first and second implantation regions, and the source region can use a same mask layer.