The semiconductor device of the present invention includes a semiconductor substrate, a switching element which is defined on the semiconductor substrate, and a temperature sense element which is provided on the surface of the semiconductor substrate independently from the switching element and characterized by being dependent on a temperature.

In certain examples, methods and semiconductor structures are directed to a semiconductor device having a circuit that includes an active region (e.g., a channel region of a transistor) and having a poly crystalline-diamond-based thermal field plate (TFP). The TFP, or a first portion thereof, is oriented over or under the active region. Further, the first portion is located in proximity to the active region for passing heat away from the active region, and includes a layer of poly crystalline-diamond grains with an average grain width dimension and an average thickness dimension, wherein the average grain width dimension and the average thickness dimension characterize the poly crystalline-diamond grains as being more isotropic than columnar. With the first portion, or the entire TFP, being in close proximity of the channel region, during operation of the circuit, the TFP passes heat away from the channel region to maintain a relatively low-temperature circuit.

A microelectronic device includes a semiconductor substrate with a III-N semiconductor layer over the semiconductor substrate. A substrate via opening extending through the III-N semiconductor layer and a substrate contact pad in the substrate via opening, contacting the semiconductor substrate provide a substrate contact. The microelectronic device also includes an inter-level dielectric layer with a planar surface over the substrate contact. The microelectronic device further includes an interconnect metal level over the inter-level dielectric layer. The substrate via opening is formed through the III-N semiconductor layer to expose the semiconductor substrate. The substrate contact pad is formed over the III-N semiconductor layer, extending into the substrate via opening and making contact with the semiconductor substrate, to form the substrate contact. The ILD layer is formed over the III-N semiconductor layer and the substrate contact pad, so that the ILD layer has a planar surface over the substrate via opening.

A semiconductor device includes a substrate, a first transistor unit having a first drain electrode, a first gate electrode, and a first source electrode, a second transistor unit having a second source electrode, a second gate electrode, and a second drain electrode, a gate wiring provided between the first source electrode and the second source electrode and electrically connected to the first gate electrode and the second gate electrode, a first cover metal layer electrically connected to the first source electrode, at least an upper portion of the first cover metal layer projecting toward the gate wiring more than the first source electrode, and a second cover metal layer electrically connected to the second source electrode, at least an upper portion of the second cover metal layer projecting toward the gate wiring more than the second source electrode.

A nitride semiconductor device includes: a substrate; a first nitride semiconductor layer provided over the substrate; a second nitride semiconductor layer that is on the first nitride semiconductor layer and includes a band gap larger than a band gap of the first nitride semiconductor layer; and a third nitride semiconductor layer that is on the second nitride semiconductor layer and includes a band gap larger than the band gap of the first nitride semiconductor layer. The second nitride semiconductor layer includes a damaged region in which an n-type impurity is selectively added by ion implantation. A diffusion region in which the n-type impurity is diffused is present in a vicinity of the damaged region. The nitride semiconductor device further includes: an ohmic electrode provided above the damaged region. The ohmic electrode is in ohmic contact with the diffusion region.

A GaN epitaxial substrate contains a GaN substrate and a GaN buffer layer epitaxially grown on the GaN substrate. The GaN epitaxial substrate includes a point A and a point B which is positioned on a straight line parallel to a [0001] axis passing through the point A, the point B being present in a [0001] axis direction relative to the point A, the point A is present in the GaN substrate or the GaN buffer layer, the point B is present in the GaN buffer layer, a ratio ([Fe].sub.B/[Fe].sub.A) is 1/100, [Fe].sub.A being a Fe concentration of the point A and [Fe].sub.B being a Fe concentration of the point B, and a distance between the point A and the point B is 0.2 m or less.

A method includes forming a first sacrificial layer over a substrate, and forming a sandwich structure over the first sacrificial layer. The sandwich structure includes a first isolation layer, a two-dimensional material over the first isolation layer, and a second isolation layer over the two-dimensional material. The method further includes forming a second sacrificial layer over the sandwich structure, forming a first source/drain region and a second source/drain region on opposing ends of, and contacting sidewalls of, the two-dimensional material, removing the first sacrificial layer and the second sacrificial layer to generate spaces, and forming a gate stack filling the spaces.

A semiconductor device includes first and second nitride semiconductor layers. The second layer on the first nitride has a first region, a second region, and a third region between the first and second regions. A first gate electrode is in the first region and extends parallel to a surface of a substrate. A first source electrode is in the first region and extends in the first direction. A second gate electrode in the second region and extends in the first direction. A second source electrode is in the second region and extends in the first direction. A drain electrode coupled to a first and a second wiring. The first wiring directly contacts the second nitride semiconductor layer in the first region. The second wiring directly contacts the second nitride semiconductor layer in the second region. An insulation material is in the third region.

A semiconductor device includes a GaN FET on a silicon substrate and a buffer layer of III-N semiconductor material, with a columnar region, a transition region surrounding the columnar region, and an inter-columnar region around the transition region. The columnar region is higher than the inter-columnar region. The GaN FET includes a gate of III-N semiconductor material with a thickness greater than twice the vertical range of the top surface of the buffer layer in the columnar region. A difference between the gate thickness over the columnar region and over the transition region is less than half of the vertical range of the top surface of the buffer layer in the columnar surface. The semiconductor device may be formed by forming a gate layer of III-N semiconductor material over the barrier layer by a gate MOVPE process using a carrier gas that includes zero to 40 percent hydrogen gas.

According to one embodiment, a nitride semiconductor includes a base body, a nitride member, and an intermediate region provided between the base body and the nitride member. The nitride member includes a first nitride region including Al.sub.x1Ga.sub.1-x1N (0<x11), and a second nitride region including Al.sub.x2Ga.sub.1-x2N (0x2<1, x2<x1). The first nitride region is between the intermediate region and the second nitride region. The intermediate region includes nitrogen and carbon. A concentration of carbon in the intermediate region is not less than 1.510.sup.19/cm.sup.3 and not more than 610.sup.20/cm.sup.3.