Systems, devices, and methods for optical sensing applications. An example multi-wavelength light emitter structure including a substrate; and a vertical structure over the substrate and extending vertically away from the substrate along an axis, the vertical structure comprising a first active region including one or more cascade stages of superlattices for light emission at a first wavelength; a second active region including one or more cascade stages of superlattices for light emission at a second wavelength different from the first wavelength, wherein the second active region is closer to the substrate than the first active region and spaced apart from the first active region; and an electrically conductive material along sidewalls of at least one of the first active region or the second active region.

An oxide sintered body which, when made into an oxide semiconductor thin film by sputtering, can achieve low carrier density and high carrier mobility, and a sputtering target using said oxide sintered body are provided. This oxide sintered body contains indium and gallium as oxides, contains nitrogen, and does not contain zinc. The gallium content in terms of the atomic ratio Ga/(In+Ga) is between 0.20 and 0.60, inclusive, and substantially no GaN phase is included. Furthermore, the sintered oxide preferably has no Ga.sub.2O.sub.3 phase. An amorphous oxide semiconductor thin film formed using this oxide sintered body as a sputtering target yields a carrier density of 3.010.sup.18 cm.sup.3 or less, and a carrier mobility of 10 cm.sup.2 V.sup.1 sec.sup.1 or more.

An oxide sintered body which, when made into an oxide semiconductor thin film by sputtering, can achieve low carrier density and high carrier mobility, and a sputtering target using said oxide sintered body are provided. This oxide sintered body contains indium and gallium as oxides, contains nitrogen, and does not contain zinc. The gallium content in terms of the atomic ratio Ga/(In+Ga) is at least 0.005 but less than 0.20, and substantially no GaN phase is included. Furthermore, the sintered oxide preferably has no Ga.sub.2O.sub.3 phase. A crystalline oxide semiconductor thin film formed using this oxide sintered body as a sputtering target yields a carrier density of 1.010.sup.18 cm.sup.3 or less, and a carrier mobility of 10 cm.sup.2V.sup.1sec.sup.1 or more.

According to example embodiments, a two-dimensional (2D) material element may include a first 2D material and a second 2D material chemically bonded to each other. The first 2D material may include a first metal chalcogenide-based material. The second 2D material may include a second metal chalcogenide-based material. The second 2D material may be bonded to a side of the first 2D material. The 2D material element may have a PN junction structure. The 2D material element may include a plurality of 2D materials with different band gaps.

Passivated semiconductor nanoparticles and methods for the fabrication and use of passivated semiconductor nanoparticles is provided herein.

Transistor structures may include a metal oxide contact buffer between a portion of a channel material and source or drain contact metallization. The contact buffer may improve control of transistor channel length by limiting reaction between contact metallization and the channel material. The channel material may be of a first composition and the contact buffer may be of a second composition.

Transistor structures may include a metal oxide contact buffer between a portion of a channel material and source or drain contact metallization. The contact buffer may improve control of transistor channel length by limiting reaction between contact metallization and the channel material. The channel material may be of a first composition and the contact buffer may be of a second composition.

The disclosure relates to a simulation method for selecting an optimal composition ratio of an oxide semiconductor. The oxide semiconductor includes at least two elements selected from the group consisting of indium (In), gallium (Ga), zinc (Zn), tin (Sn), silver (Ag), aluminum (Al), cadmium (Cd), magnesium (Mg), antimony (Sb), silicon (Si), titanium (Ti), and zirconium (Zr); oxygen (O); and inevitable impurities. The simulation method includes setting a simulation target composition ratio set including various composition ratios of elements constituting the oxide semiconductor, checking whether the oxide semiconductor satisfies Formulas 1, 2, and 3 for each of the various composition ratios included in the simulation target composition ratio set, and selecting a composition ratio satisfying Formulas 1, 2, and 3 as an optimal composition ratio. Formulas 1, 2, and 3 may be the same as described in the specification.

The disclosure relates to a simulation method for selecting an optimal composition ratio of an oxide semiconductor. The oxide semiconductor includes at least two elements selected from the group consisting of indium (In), gallium (Ga), zinc (Zn), tin (Sn), silver (Ag), aluminum (Al), cadmium (Cd), magnesium (Mg), antimony (Sb), silicon (Si), titanium (Ti), and zirconium (Zr); oxygen (O); and inevitable impurities. The simulation method includes setting a simulation target composition ratio set including various composition ratios of elements constituting the oxide semiconductor, checking whether the oxide semiconductor satisfies Formulas 1, 2, and 3 for each of the various composition ratios included in the simulation target composition ratio set, and selecting a composition ratio satisfying Formulas 1, 2, and 3 as an optimal composition ratio. Formulas 1, 2, and 3 may be the same as described in the specification.

A semiconductor device with a high on-state current and high operating speed is provided. The semiconductor device includes a transistor and a first circuit. The transistor includes a first gate and a second gate, and the first gate and the second gate include a region where they overlap each other with a semiconductor layer therebetween. The first circuit includes a temperature sensor and a voltage control circuit. The temperature sensor has a function of obtaining temperature information and outputting the temperature information to the voltage control circuit. The voltage control circuit has a function of converting the temperature information into a control voltage. The first circuit applies the control voltage to the second gate.