A power chip, includes a metal region; a wafer region. The wafer region includes at least one first partition, forming a first power switch; and at least one second partition, forming a second power switch. The first power switch and the second power switch are electrically connected, a total number of the at least one first partition and the at least one second partition is not less than 3, and the at least one first partition and the at least one second partition are disposed alternatively along a curve.

A p-type oxide which is amorphous and is represented by the following compositional formula: xAO.yCu.sub.2O where x denotes a proportion by mole of AO and y denotes a proportion by mole of Cu.sub.2O and x and y satisfy the following expressions: 0x<100 and x+y=100, and A is any one of Mg, Ca, Sr and Ba, or a mixture containing at least one selected from the group consisting of Mg, Ca, Sr and Ba.

The method of manufacturing a semiconductor device, including preparing a semiconductor substrate, forming a first insulating layer over said semiconductor substrate, forming first grooves in the first insulating film, forming a gate electrode and a first interconnect in the first grooves, respectively, forming a gate insulating film over the gate electrode, forming a semiconductor layer over the gate insulating, forming a second insulating layer over the semiconductor layer and the first insulating film, forming a via in the second insulating layer, and forming a second interconnect such that the second interconnect is connected to the semiconductor layer through the via. The gate electrode, the first interconnect and the second interconnect are formed by Cu or Cu alloy, respectively.

The invention generally relates to methods of thermal doping by vacancy formation in nanocrystals, devices and uses thereof.

A two-dimensional electronic component includes a substrate; an artificial two-dimensional (2D) material disposed on the substrate; and a first metallic electrode disposed on the artificial 2D material. The artificial 2D material includes a layered atomic structure including a middle atomic layer, a lower atomic layer disposed on a lower surface of the middle atomic layer, and an upper atomic layer disposed on an upper surface of the middle atomic layer respectively. The upper atomic layer and the first metallic electrode are attracted together at a junction therebetween by metallic bonding.

A semiconductor device includes a substrate, a two-dimensional (2D) material layer formed on the substrate and having a first region and a second region adjacent to the first region, and a source electrode and a drain electrode provided to be respectively in contact with the first region and the second region of the 2D material layer, the second region of the 2D material layer including an oxygen adsorption material layer in which oxygen is adsorbed on a surface of the second region.

A gas sensor including a first layer including copper (I) bromide, and a second layer, which is disposed on the first layer, and is a p-type semiconductor that is different from the copper (I) bromide, wherein one of the first layer and the second layer is more preferentially in contact with detection-target gas than the other.

A two-dimensional thin film transistor and a method for manufacturing a two-dimensional thin film transistor includes layering a semiconducting channel material on a substrate, providing a first electrode material on top of the semiconducting channel material, patterning a source metal electrode and a drain metal electrode at opposite ends of the semiconducting channel material from the first electrode material, opening a window between the source metal electrode and the drain metal electrode, removing the first electrode material from the window located above the semiconducting channel material providing a gate dielectric above the semiconducting channel material, and providing a top gate above the gate dielectric, the top gate formed from a second electrode material. The semiconducting channel material is made of tungsten diselenide, the first electrode material and the second electrode material are made of graphene, and the gate dielectric is made of hexagonal boron nitride.

A thin-film transistor comprises a substrate, a first electrode on the top surface of the substrate, an insulation layer on the top surface of the substrate and covering the first electrode, a semiconductor oxide layer on the top surface of the insulation layer, a protection layer on the top surface of the semiconductor oxide layer, an organic dielectric layer on the top surface of the semiconductor oxide layer and covering the protection layer, a source electrode and a drain electrode both penetrating the organic dielectric layer from the top surface thereof. A channel thickness of the semiconductor oxide layer is not thicker than 20 nanometers. The source electrode contacts the semiconductor oxide layer at the first side of the protection layer and the drain electrode contacts the semiconductor oxide layer at the second side, opposite to the first side, of the protection layer.

A semiconductor memory device includes a plurality of transistors disposed along a major surface of a substrate, a plurality of metallization layers including a plurality of metal tracks and disposed over the major surface of the substrate, and a plurality of memory cells formed within one or more of the metallization layers. At least one of the plurality of transistors is electrically coupled to the plurality of memory cells. Each of the plurality of memory cells includes an access transistor and a storage capacitor electrically coupled to each other in series and physically arranged with respect to each other along a vertical direction.