The present disclosure relates to vertical field effect transistors (FET). The vertical FET according to the invention includes a substrate (101) and a first electrode (102) configured as either a source or a drain of the transistor. The device includes a second electrode (104) configured as the other of the source and the drain, where the second electrode at least partially overlaps the first electrode in an overlapping region. Moreover, the device comprises an active layer (103) that is sandwiched between the first electrode and the second electrode and a gate arrangement including a gate conductor portion (107) and a gate insulating layer (106), which is arranged between the active layer (103) and a gate conductor portion (107) so as to prevent direct contact between the active layer (103) and the gate conductor portion (107). The active layer (103) comprises a 1D material arranged with its longitudinal axis parallel to the substrate (101) and/or a 2D material arranged with its plane substantially parallel to the substrate (101) The present disclosure further comprises a method (3000) for the manufacture of such vertical field effect transistors as well as for the manufacture of complementary logic devices.

A method for producing a device comprising GAA transistors. Advantageously, the channels of the transistors are produced by deposition of a semiconductor material, preferably a 2D material, after successive removal of certain layers of the initial stack. The gates-all-around are produced after selective removal of the other layers from the initial stack. The initial stack does not comprise the semiconductor material, nor the material of the gates. The subsequent deposition of the semiconductor material aims to better preserve the semiconductor material.

Provided is a manufacturing method of a Van der Waals contact semiconductor device, which includes arranging and patterning a first material on a first substrate; arranging and patterning a second material on a second substrate; and transferring the second material onto the first material, in which any one of the first material and the second material is a topological insulator (TI), and the other one includes a two-dimensional semiconductor material, and the first material and the second material are subjected to Van der Waals contact.

The invention relates to a device comprising transistors (T1, T2, T3), each comprising: a channel (41) with the basis of a semiconductive material, a gate-all-around (50), totally surrounding said channel (41), a source (42) and a drain (43) on either side of the channel (41), and source and drain contacts (60S, 60, 60D), a gate dielectric layer (30) separating the channel (41) and the gate-all-around (50), spacers (70) on either side of the gate (50). Advantageously, the gate dielectric layer (30) and the spacers (70) are formed by at least one single and same continuous layer (73) surrounding the gate-all-around (50). The invention also relates to a method for producing such a device.

The invention relates to a microelectronic device comprising a transistor (T1, T2) comprising

at least two channels (41a, 41b, 41c) stacked along a main direction (z),. a first gate (G1) partially surrounding one of the channels (41a, 41b, 41c),

a second gate (G2) partially surrounding said channel (41),

a source (42) and a drain (43) either side of the channels (41a, 41b, 41c), and source and drain contacts (60S, 60, 60D) connected respectively to the source (42) and to the drain (43),

a gate dielectric layer (70, 71, 72) separating each channel (41) of the gates-all-around (G1, G2).

The first and second gates (G1, G2) are isolated from one another, such that they can be independently biased.

The invention also relates to a method for producing such a device.

A device comprising two transistors stacked along a main direction, the first transistor comprising channels stacked along the main direction and first source and drain contacts, the second transistor comprising channels stacked along the main direction and second source and drain contacts, wherein the first source (respectively drain) contact and the second source (respectively drain) contact are distinct and isolated from one another by a first gate dielectric layer and by a second gate dielectric layer. The invention also relates to a method for manufacturing the device.

An embodiment relates to a method for controlling the surface characteristics and thickness of a multilayer transition metal dichalcogenide thin film. By forming an amorphous transition metal oxide thin film on a multilayer transition metal dichalcogenide thin film, and then treating the multilayer transition metal dichalcogenide thin film having the amorphous transition metal oxide thin film formed thereon with an aqueous solution of ammonium sulfide at least once, the surface characteristics and thickness of the transition metal dichalcogenide can be controlled in a simple and low-cost manner without complex equipment settings for heat treatment, plasma and laser etching, and so on.

Disclosed are a high-mobility atomic layer semiconductor device based on modulation doping and a method for fabricating the same, which prevent a charge scattering phenomenon caused by ionized impurities by modulation doping dopants such that the dopants are spatially separated from a channel layer of an atomic layer semiconductor device having an atomic layer semiconductor heterojunction structure band-aligned. According to an embodiment of the present disclosure, a high-mobility atomic layer semiconductor device based on modulation doping includes a substrate, an atomic layer semiconductor heterojunction structure band-aligned in type I or type II and including a channel layer allowing movement of an electron and a doping layer, wherein the channel layer and the doping layer are stacked on the substrate, and a dopant formed on the doping layer and including a material for supplying an electron or a hole to the channel layer. The dopant is doped while being spatially separated from the channel layer through the doping layer, instead of being directly doped into the channel layer.

An embodiment relates to a method for controlling the surface characteristics and thickness of a multilayer transition metal dichalcogenide thin film. By forming an amorphous transition metal oxide thin film on a multilayer transition metal dichalcogenide thin film, and then treating the multilayer transition metal dichalcogenide thin film having the amorphous transition metal oxide thin film formed thereon with an aqueous solution of ammonium sulfide at least once, the surface characteristics and thickness of the transition metal dichalcogenide can be controlled in a simple and low-cost manner without complex equipment settings for heat treatment, plasma and laser etching, and so on.

The present disclosure relates to vertical field effect transistors (FET). The vertical FET according to the invention includes a substrate (101) and a first electrode (102) configured as either a source or a drain of the transistor. The device includes a second electrode (104) configured as the other of the source and the drain, where the second electrode at least partially overlaps the first electrode in an overlapping region. Moreover, the device comprises an active layer (103) that is sandwiched between the first electrode and the second electrode and a gate arrangement including a gate conductor portion (107) and a gate insulating layer (106), which is arranged between the active layer (103) and a gate conductor portion (107) so as to prevent direct contact between the active layer (103) and the gate conductor portion (107). The active layer (103) comprises a 1D material arranged with its longitudinal axis parallel to the substrate (101) and/or a 2D material arranged with its plane substantially parallel to the substrate (101) The present disclosure further comprises a method (3000) for the manufacture of such vertical field effect transistors as well as for the manufacture of complementary logic devices.