In some embodiments, the present disclosure relates to an integrated chip structure. The integrated chip structure includes a first doped region and a second doped region disposed within a substrate. A data storage structure is arranged over the substrate and laterally between the first doped region and the second doped region. An isolation structure is arranged within the substrate along a first side of the data storage structure. The first doped region is laterally between the isolation structure and the data storage structure. A remnant is arranged over and along a sidewall of the isolation structure. The remnant includes a first material having a vertically extending segment and a horizontally extending segment protruding outward from a sidewall of the vertically extending segment.

A method for forming a semiconductor structure includes the following steps. A semiconductor device is formed over a substrate. A trench is formed in the semiconductor device. The trench is filled with a gap-fill material using a deposition process, wherein a precursor used in the deposition process includes azidosilane, di-azidosilane or halide azidosilane.

A semiconductor structure and a method of forming the same are provided. In an embodiment, an exemplary method includes forming a fin-shaped active region over a substrate and comprising a number of channel layers interleaved by a number of sacrificial layers, removing a source/drain region of the fin-shaped active region to form a source/drain opening, forming a source/drain feature in the source/drain opening, selectively removing the number of sacrificial layers to form a number of gate openings, and forming a gate structure in the number of gate openings, where the gate structure includes a first portion formed in a first gate opening of the number of gate openings and a second portion formed in a second gate opening of the number of gate openings, a gate length of the first portion is different from a gate length of the second portion.

Inner spacers between a source/drain region of a nanostructure transistor and sacrificial nanostructure layers of the nanostructure transistor are removed prior to formation of a gate structure of the nanostructure transistor. The sacrificial nanostructure layers are removed, and then the inner spacers are removed. The sacrificial nanostructure layers are then replaced with the gate structure of the nanostructure transistor such that the gate structure and the source/drain region are spaced apart by air gaps that result from the removal of the inner spacers. The dielectric constant (or relative permittivity) of the air gaps between the source/drain region and the gate structure is less than the dielectric constant of the material of the inner spacers. The lesser dielectric constant of the air gaps reduces the amount of capacitance between the source/drain region and the gate structure.

Provided are a semiconductor device and a method for forming the same. The semiconductor device includes a substrate including first and second active regions defined by an element isolation structure, a first element in the first active region and including a gate structure on the substrate, a second element in the second active region and including an insulation pattern in the substrate and including a first portion and a second portion surrounding the first portion, and a dummy gate structure in the second active region and including first and second patterns respectively on the first and second portions and a third pattern on the device isolation structure. The second portion and the element isolation structure define a region where a first doped region of the second element is formed. The second portion and the first portion define a region where a second doped region of the second element is formed.

In some embodiments, the present disclosure relates to an integrated chip that includes a channel structure extending between a first source/drain region and a second source/drain region. Further, a gate electrode is arranged directly over the channel structures, and an upper interconnect contact is arranged over and coupled to the gate electrode. A backside contact is arranged below and coupled to the first source/drain region. The backside contact has a width that decreases from a bottommost surface of the backside contact to a topmost surface of the backside contact.

Gate contact structures disposed over active portions of gates and methods of forming such gate contact structures are described. For example, a semiconductor structure includes a substrate having an active region and an isolation region. A gate structure has a portion disposed above the active region and a portion disposed above the isolation region of the substrate. Source and drain regions are disposed in the active region of the substrate, on either side of the portion of the gate structure disposed above the active region. A gate contact structure is disposed on the portion of the gate structure disposed above the active region of the substrate.

A method includes forming a first bottom-tier transistor; forming a second bottom-tier transistor, the first and second bottom-tier transistors sharing a same source/drain region; forming a first top-tier transistor over the first bottom-tier transistor, the first top-tier transistor comprising a first channel layer and a first gate structure around the first channel layer; forming a second top-tier transistor over the second bottom-tier transistor, the second top-tier transistor comprising a second channel layer and a second gate structure around the second channel layer, the first and second top-tier transistors sharing a same source/drain region, wherein from a top view, a first dimension of the first channel layer in a lengthwise direction of the first gate structure is different than a second dimension of the second channel layer in the lengthwise direction of the first gate structure.

A method includes forming first, second, third, fourth, fifth, and sixth channel patterns on a semiconductor substrate; forming a first isolation wall interposing the first and second channel patterns, a second isolation wall interposing the third and fourth channel patterns, wherein the first isolation wall further continuously extends to interpose the fifth and sixth channel patterns; forming a first gate pattern extending across the first, second, third, and fourth channel patterns and the first and second isolation walls, and a second gate pattern extending across the fifth and sixth channel patterns and the first isolation wall from the top view, wherein the first, second, third, fourth, and sixth channel patterns respectively have first, second, third, fourth, and sixth dimensions in a lengthwise direction of the first gate pattern, and the sixth dimension is greater than the first, second, third, and fourth dimensions.

A semiconductor cell comprises a top FET that contains a first set of silicon nanosheets and a bottom FET that contains a second set of silicon nanosheets. The top FET and bottom FET are in a stacked profile. The semiconductor cell comprises a top FET cutout region lateral to the first set of nanosheets and above a portion of the second set of nanosheets. The semiconductor cell also comprises a dielectric fill within the top FET cutout region.