In some embodiments, the present disclosure relates to an integrated chip structure. The integrated chip structure includes a first doped region and a second doped region disposed within a substrate. A data storage structure is arranged over the substrate and laterally between the first doped region and the second doped region. An isolation structure is arranged within the substrate along a first side of the data storage structure. The first doped region is laterally between the isolation structure and the data storage structure. A remnant is arranged over and along a sidewall of the isolation structure. The remnant includes a first material having a vertically extending segment and a horizontally extending segment protruding outward from a sidewall of the vertically extending segment.

The present disclosure relates to semiconductor structures and, more particularly, to an extended drain metal oxide semiconductor (EDMOS) field effect transistor (FET) with a fully depleted region comprising a dual thicknesses semiconductor material and methods of manufacture. The structure includes: a semiconductor on insulator (SOI) material including a first portion with a first thickness and a second portion with a second thickness; a gate structure on the SOI material over the first portion with the first thickness; and sidewall spacers adjacent to the gate structure, with at least one sidewall spacer extending over both the first portion with the first thickness and the second portion with the second thickness.

A transistor device and method of fabrication are provided, where the transistor device may include a semiconductor substrate, a first dielectric layer disposed on a surface of the semiconductor substrate, a second dielectric layer disposed directly on the first dielectric layer, a gate structure disposed directly on the surface of the semiconductor substrate, and a spacer structure. A first opening through the first dielectric layer and the second dielectric layer may correspond to a gate channel. Portions of the first dielectric layer and the second dielectric layer may be interposed directly between portions of the gate structure and the surface of the semiconductor substrate. The spacer structure may be disposed in the gate channel and interposed between the gate structure and the semiconductor substrate. The spacer structure may contact respective side surfaces of the first dielectric layer and the second dielectric layer that at least partially define the gate channel.

A semiconductor device comprises a top field effect transistor (FET) and a bottom FET in a stacked profile. The semiconductor device also comprises a gate. The gate comprises two top-FET gate extensions and two bottom-FET gate extensions. The semiconductor device also comprises an insulator liner. The insulator liner interfaces with the two top-FET gate extensions and two bottom-FET gate extensions. The semiconductor device also comprises a dielectric that interfaces with the insulator liner.

A semiconductor device includes an active pattern including a lower pattern extending a first direction and a plurality of sheet patterns spaced apart from the lower pattern in a second direction, the plurality of sheet patterns including an uppermost sheet pattern, a plurality of gate structures disposed to be spaced apart from each other in the first direction on the active pattern and including gate electrodes extending in a third direction and gate spacers on sidewalls of the gate electrodes and a source/drain pattern disposed between the gate structures adjacent to each other and including a semiconductor liner film and a semiconductor filling film on the semiconductor liner film, wherein the semiconductor liner film covers a portion of an upper surface of an uppermost sheet pattern.

A semiconductor device includes a substrate, a bit line structure formed over and protruding from the substrate, a spacer structure formed on and extending along sidewall of the bit line structure, and a landing pad disposed on the bit line structure and covering the slope. The spacer structure includes a first segment near a top of the spacer structure with a slope and a second segment beneath the first segment. A first segment consists of a first spacer layer contacting the bit line structure and a third spacer layer contacting the first spacer layer. A second segment consists of the first spacer layer contacting the bit line structure, a second spacer layer contacting the first spacer layer, and the third spacer layer contacting the second spacer layer, and the second segment is capped with the first segment.

A method for manufacturing a gate-all-around TFET device. The method comprises: forming, on a substrate, a channel stack comprising channel layer(s) and sacrificial layer(s) that alternate with each other; forming, on the substrate, a dummy gate astride the channel stack; forming a first spacer at a surface of the dummy gate; etching the sacrificial layer(s) to form recesses on side surfaces of the channel stack; forming second spacers in the recesses, respectively; fabricating a source and a drain separately, where a region for fabricating the source is shielded by a dielectric material when fabricating the drain, and a region for fabricating the drain is shielded by another dielectric material when fabricating the source; etching the dummy gate and the sacrificial layer(s) to form a space for a surrounding gate; and fabricating a surrounding dielectric-metal gate in the space.

In an embodiment, a device includes: a first word line over a substrate, the first word line including a first conductive material; a first bit line intersecting the first word line; a first memory film between the first bit line and the first word line; and a first conductive spacer between the first memory film and the first word line, the first conductive spacer including a second conductive material, the second conductive material having a different work function than the first conductive material, the first conductive material having a lower resistivity than the second conductive material.

Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary method comprises forming first and second semiconductor fins in first and second regions of a substrate, respectively; forming first and second dummy gate stacks over the first and second semiconductor fins, respectively, and forming a spacer layer over the first and the second dummy gate stacks; forming a first pattern layer with a thickness along the spacer layer in the first region; form a first source/drain (S/D) trench along the first pattern layer and epitaxially growing a first epitaxial feature therein; removing the first pattern layer to expose the spacer layer; forming a second pattern layer with a different thickness along the spacer layer in the second region; form a second S/D trench along the second pattern layer and epitaxially growing a second epitaxial feature therein; and removing the second pattern layer to expose the spacer layer.

Semiconductor structures and methods of forming the same are provided. An example semiconductor structure includes a fin structure arising from a substrate and extending lengthwise along a direction, an isolation feature over the substrate and around the fin structure, a gate structure wrapping over a channel region of the fin structure, a first gate spacer extending along a sidewall of the gate structure, a second gate spacer over the first gate spacer, a filler dielectric layer over the second gate spacer, an epitaxial feature disposed over a source/drain region of the fin structure, a portion of the epitaxial feature being disposed over the filler dielectric layer, an contact etch stop layer (CESL) over the epitaxial feature and the filler dielectric layer, and an interlayer dielectric (ILD) layer over the CESL. A portion of the CESL extends between the epitaxial feature and the sidewall of gate structure along the direction.