In some embodiments, the present disclosure relates to an integrated chip structure. The integrated chip structure includes a first doped region and a second doped region disposed within a substrate. A data storage structure is arranged over the substrate and laterally between the first doped region and the second doped region. An isolation structure is arranged within the substrate along a first side of the data storage structure. The first doped region is laterally between the isolation structure and the data storage structure. A remnant is arranged over and along a sidewall of the isolation structure. The remnant includes a first material having a vertically extending segment and a horizontally extending segment protruding outward from a sidewall of the vertically extending segment.

Technologies for a field effect transistor (FET) with a ferroelectric gate dielectric are disclosed. In an illustrative embodiment, a transistor includes a gate of strontium ruthenate and a ferroelectric gate dielectric layer of barium titanate. In order to prevent migration of ruthenium from the strontium ruthenate to the barium titanate, a barrier layer is placed between the gate and the ferroelectric gate dielectric layer. The barrier layer may be a metal oxide, such as strontium oxide, barium oxide, zirconium oxide, etc.

In an embodiment, a device includes: a first word line over a substrate, the first word line including a first conductive material; a first bit line intersecting the first word line; a first memory film between the first bit line and the first word line; and a first conductive spacer between the first memory film and the first word line, the first conductive spacer including a second conductive material, the second conductive material having a different work function than the first conductive material, the first conductive material having a lower resistivity than the second conductive material.

A semiconductor device has, in a gate insulating layer, in an XPS spectrum of O 1s obtained by an X-ray photoelectron spectroscopy (XPS) using a monochromatic aluminum K (1486.6 eV) source, a ratio (%) of an AlO peak observed in a binding energy of about 530.3 eV to about 531.6 eV to all peaks of greater than or equal to about 80%.

A semiconductor device includes a transistor and a ferroelectric tunnel junction. The ferroelectric tunnel junction is connected to a drain contact of the transistor. The ferroelectric tunnel junction includes a first electrode, a second electrode, a crystalline oxide layer, and a ferroelectric layer. The second electrode is disposed over the first electrode. The crystalline oxide layer and the ferroelectric layer are disposed in direct contact with each other in between the first electrode and the second electrode. The crystalline oxide layer comprises a crystalline oxide material. The ferroelectric layer comprises a ferroelectric material.

A semiconductor memory device includes a semiconductor layer; a gate electrode; a first insulating film provided between the semiconductor layer and the gate electrode, and including at least one of oxygen, hafnium, or a first additive element; and a second insulating film provided between the first insulating film and the gate electrode. The first insulating film includes a first additive region, a second additive region provided between the first additive region and the gate electrode, and a memory region provided between the first additive region and the second additive region. The first additive region includes a second additive element selected from a group consisting of ruthenium, titanium, molybdenum, tantalum, tungsten, platinum, and combinations thereof. The second additive region includes a third additive element selected group consisting of ruthenium, titanium, molybdenum, tantalum, tungsten, platinum, and combinations thereof.

In an embodiment, a device includes: a first dielectric layer over a substrate; a word line over the first dielectric layer, the word line including a first main layer and a first glue layer, the first glue layer extending along a bottom surface, a top surface, and a first sidewall of the first main layer; a second dielectric layer over the word line; a first bit line extending through the second dielectric layer and the first dielectric layer; and a data storage strip disposed between the first bit line and the word line, the data storage strip extending along a second sidewall of the word line.

In some embodiments, the present disclosure relates to a method of forming an integrated chip including forming a ferroelectric layer over a bottom electrode layer, forming a top electrode layer over the ferroelectric layer, performing a first removal process to remove peripheral portions of the bottom electrode layer, the ferroelectric layer, and the top electrode layer, and performing a second removal process using a second etch that is selective to the bottom electrode layer and the top electrode layer to remove portions of the bottom electrode layer and the top electrode layer, so that after the second removal process the ferroelectric layer has a surface that protrudes past a surface of the bottom electrode layer and the top electrode layer.

A device includes a multi-layer stack, a channel layer, a ferroelectric layer and buffer layers. The multi-layer stack is disposed on a substrate and includes a plurality of conductive layers and a plurality of dielectric layers stacked alternately. The channel layer penetrates through the plurality of conductive layers and the plurality of dielectric layers. The ferroelectric layer is disposed between the channel layer and each of the plurality of conductive layers and the plurality of dielectric layers. The buffer layers include a metal oxide, and one of the buffer layers is disposed between the ferroelectric layer and each of the plurality of dielectric layers.

A Semiconductor device includes a semiconductor substrate, an insulating film, a first conductive film, a ferroelectric film, an insulating layer, a first plug and a second plug. The semiconductor substrate includes a source region and a drain region which are formed on a main surface thereof. The insulating film is formed on the semiconductor substrate such that the insulating film is located between the source region and the drain region in a plan view. The first conductive film is formed on the insulating film. The ferroelectric film is formed on the first conductive film. The insulating layer covers the first conductive film and the ferroelectric film. The first plug reaches the first conductive film. The second plug reaches the ferroelectric film. A material of the ferroelectric film includes hafnium and oxygen. In plan view, a size of the ferroelectric film is smaller than a size of the insulating film.