A transistor device and method of fabrication are provided, where the transistor device may include a semiconductor substrate, a first dielectric layer disposed on a surface of the semiconductor substrate, a second dielectric layer disposed directly on the first dielectric layer, a gate structure disposed directly on the surface of the semiconductor substrate, and a spacer structure. A first opening through the first dielectric layer and the second dielectric layer may correspond to a gate channel. Portions of the first dielectric layer and the second dielectric layer may be interposed directly between portions of the gate structure and the surface of the semiconductor substrate. The spacer structure may be disposed in the gate channel and interposed between the gate structure and the semiconductor substrate. The spacer structure may contact respective side surfaces of the first dielectric layer and the second dielectric layer that at least partially define the gate channel.

A transistor device and method of fabrication are provided, where the transistor device may include a first dielectric layer disposed on a surface of the semiconductor substrate, a second dielectric layer disposed directly on the first dielectric layer, a third dielectric layer disposed on the second dielectric layer, a gate structure disposed directly on the surface of the semiconductor substrate in the gate channel, and a field plate disposed overlapping the gate structure. The gate may be defined via an opening that extends through the first, second, and third dielectric layers. Portions of the first and second dielectric layers may be interposed directly between the gate structure and the surface of the semiconductor substrate. A portion of the field plate may be disposed in a field plate channel at least partially defined via a second opening that extends through the second dielectric layer and the third dielectric layer.

A semiconductor device includes a semiconductor body having opposing first and second surfaces along a vertical direction, and a bipolar junction transistor that includes an emitter region electrically connected to an emitter contact at the first surface, a base region electrically connected to a base contact at the first surface, and a collector region electrically connected to a collector contact. A dielectric isolation structure extends into the semiconductor body from the first surface and includes a first sub-structure arranged, along a first lateral direction, between the emitter contact and the base contact. A field plate structure including a field plate dielectric and a field plate electrode is arranged on the field plate dielectric. A first part of the field plate structure is arranged on the first surface of the semiconductor body. A second part of the field plate structure is arranged on the first sub-structure of the dielectric isolation structure.

A semiconductor device includes a substrate, a first transistor unit having a first drain electrode, a first gate electrode, and a first source electrode, a second transistor unit having a second source electrode, a second gate electrode electrically, and a second drain electrode, a gate wiring provided on the substrate between the first source electrode and the second source electrode and electrically connected to the first gate electrode and the second gate electrode, a first cover metal layer provided above the substrate between the first source electrode and the gate wiring and adjacent to the first source electrode and the gate wiring, and electrically connected to the first source electrode, and a second cover metal layer provided above the substrate between the second source electrode and the gate wiring and adjacent to the second source electrode and the gate wiring, and electrically connected to the second source electrode.

A method for manufacturing a semiconductor device includes: providing a semiconductor substrate; epitaxially growing a first semiconductor layer coupled to the semiconductor substrate; epitaxially growing a second semiconductor layer coupled to the first semiconductor layer, wherein the second semiconductor layer comprises a contact region and a terminal region surrounding the contact region; forming a mask layer on the second semiconductor layer, wherein the mask layer is patterned with a tapered region aligned with the terminal region of the second semiconductor layer; implanting ions into the terminal region of the second semiconductor layer using the mask layer to form a tapered junction termination element in the terminal region of the second semiconductor layer; and forming a contact structure in the contact region of the second semiconductor layer.

In an embodiment, a Group III nitride-based transistor device includes a first passivation layer arranged on a first major surface of a Group III nitride-based layer, a second passivation layer arranged on the first passivation layer, a source ohmic contact, a drain ohmic contact and a gate positioned on the first major surface of a Group III nitride-based layer, and a field plate, the field plate being laterally arranged between and spaced apart from the gate and the drain ohmic contact.

A switched-mode power supply includes a power semiconductor device that includes a semiconductor body comprising transistor cells and a drift zone between a drain layer and the transistor cells, the transistor cells comprising source zones, wherein the device exhibits a first output charge gradient when a voltage between the drain layer and the source zones of the transistor cells increases from a depletion voltage of the semiconductor device to a maximum drain/source voltage of the semiconductor device, wherein the device exhibits a second output charge gradient when a voltage between the drain layer and the source zones of the semiconductor device decreases from the maximum drain/source voltage to the depletion voltage of the semiconductor device, and wherein the semiconductor device is configured such that the first output charge gradient deviates by less than 5% from the second output charge gradient.

Transistor devices having metal structures with rounded corners are provided. In one example, The transistor device includes a Group III-nitride semiconductor structure. The transistor device includes a gate contact and/or a field plate on the Group III-nitride semiconductor structure. One or more of the gate contact or the field plate includes at least one rounded corner.

An embodiment of a semiconductor device includes a semiconductor substrate, a first dielectric layer, a first current-carrying electrode, and a second current-carrying electrode formed over the semiconductor substrate. A control electrode is formed over the semiconductor substrate and disposed between the first current-carrying electrode and the second current-carrying electrode. A conductive element formed over the first dielectric layer, adjacent the control electrode, and between the control electrode and the second current-carrying electrode, includes a first region formed a first distance from the upper surface of the semiconductor substrate and a second region formed a second distance from the upper surface of the semiconductor substrate. An insulating region is formed between the control electrode and the conductive element.

The present disclosure relates to semiconductor structures and, more particularly, to metal-oxide semiconductor transistors and methods of manufacture. The structure includes: a substrate comprising a drift region and a body region; a gate structure between the drift region and the body region; an insulator material over the gate structure, the drift region and the body region; and an air gap within the insulator material and extending into the drift region.